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src/tools/importer/vhdl_deriving_yojson.ml
45 45
  | Type of {name : string ; definition: vhdl_type_t} [@name "TYPE_DECLARATION"]
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  | Subtype of {name : string ; typ : vhdl_subtype_indication_t} [@name "SUBTYPE_DECLARATION"]
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[@@deriving yojson {strict = false}];;
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type vhdl_declaration_t =
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  | VarDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "VARIABLE_DECLARATION"]
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  | CstDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t  } [@name "CONSTANT_DECLARATION"]
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  | SigDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "SIGNAL_DECLARATION"]
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type vhdl_parameter_t =
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  {
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    names: string list;
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    mode: string [@default ""];
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    typ: vhdl_subtype_indication_t;
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    init_val: cst_val_t option [@default Some (CstInt (0))];
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  }
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[@@deriving yojson {strict = false}];;
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type vhdl_subprogram_spec_t =
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  {
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    name: string [@default ""];
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    typeMark: string [@default ""];
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    parameters: vhdl_parameter_t list;
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    isPure: bool [@default false];
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  }
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[@@deriving yojson {strict = false}];;
54 66

  
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(************************************************************************************)		   
......
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  | Time of { value: int; phy_unit: string [@default ""]}
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  | Sig of { name: string; att: vhdl_signal_attributes_t option }
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  | SuffixMod of { expr : vhdl_expr_t; selection : suffix_selection_t }
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  | Aggregate of { elems : vhdl_element_assoc_t list } [@name "AGGREGATE"]
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  | Others [@name "OTHERS"]
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[@@deriving yojson {strict = false}]
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and					     
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vhdl_name_t =
......
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    actual_designator: vhdl_name_t option [@default Some NoName];
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    actual_expr: vhdl_expr_t option [@default Some IsNull];
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  }
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[@@deriving yojson {strict = false}]
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and vhdl_element_assoc_t =
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  {
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    choices: vhdl_expr_t list;
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    expr: vhdl_expr_t;
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  }
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[@@deriving yojson {strict = false}];;
116 136

  
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let arith_funs = ["+";"-";"*";"/";"mod"; "rem";"abs";"**";"&"]
......
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let shift_funs = ["sll";"srl";"sla";"sra";"rol";"ror"]
121 141

  
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type vhdl_sequential_stmt_t = 
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  | VarAssign of { lhs: vhdl_name_t; rhs: vhdl_expr_t }
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  | VarAssign of { label: string [@default ""]; lhs: vhdl_name_t; rhs: vhdl_expr_t } [@name "VARIABLE_ASSIGNMENT_STATEMENT"]
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  | SigSeqAssign of { label: string [@default ""]; lhs: vhdl_name_t; rhs: vhdl_expr_t list} [@name "SIGNAL_ASSIGNMENT_STATEMENT"]
125 145
  | If of { label: string [@default ""]; if_cases: vhdl_if_case_t list;
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    default: vhdl_sequential_stmt_t list [@default []]; } [@name "IF_STATEMENT"]
......
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    when_stmt: vhdl_sequential_stmt_t list;
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  }
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[@@deriving yojson {strict = false}];;
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type vhdl_declaration_t =
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  | VarDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "VARIABLE_DECLARATION"]
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  | CstDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t  } [@name "CONSTANT_DECLARATION"]
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  | SigDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "SIGNAL_DECLARATION"]
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  | Subprogram of {name: string; kind: string; spec: vhdl_subprogram_spec_t ; decl_part: vhdl_declaration_t list; stmts: vhdl_sequential_stmt_t list} [@name "SUBPROGRAM_BODY"]
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[@@deriving yojson {strict = false}];;
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type signal_condition_t =
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  {                            
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    expr: vhdl_expr_t list;              (* when expression *)

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