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Revision d4175560 src/backends/VHDL/vhdl_ast_map.ml

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src/backends/VHDL/vhdl_ast_map.ml
333 333
        | VarDecl { names; typ; init_val } ->
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            let names = self#list self#vhdl_name_t names  in
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            let typ = self#vhdl_subtype_indication_t typ  in
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            let init_val = self#option self#vhdl_cst_val_t init_val  in
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            let init_val = self#vhdl_expr_t init_val  in
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            VarDecl { names; typ; init_val }
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        | CstDecl { names; typ; init_val } ->
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            let names = self#list self#vhdl_name_t names  in
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            let typ = self#vhdl_subtype_indication_t typ  in
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            let init_val = self#vhdl_cst_val_t init_val  in
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            let init_val = self#vhdl_expr_t init_val  in
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            CstDecl { names; typ; init_val }
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        | SigDecl { names; typ; init_val } ->
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            let names = self#list self#vhdl_name_t names  in
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            let typ = self#vhdl_subtype_indication_t typ  in
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            let init_val = self#option self#vhdl_cst_val_t init_val  in
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            let init_val = self#vhdl_expr_t init_val  in
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            SigDecl { names; typ; init_val }
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        | Subprogram { name; kind; spec; decl_part; stmts } ->
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            let name = self#vhdl_name_t name  in

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