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Revision d4175560 src/backends/VHDL/vhdl_ast.ml

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src/backends/VHDL/vhdl_ast.ml
182 182
  | VarDecl of {
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : vhdl_cst_val_t option [@default None] 
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      init_val : vhdl_expr_t [@default IsNull] 
186 186
    } [@name "VARIABLE_DECLARATION"]
187 187
  | CstDecl of { 
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : vhdl_cst_val_t 
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      init_val : vhdl_expr_t
191 191
    } [@name "CONSTANT_DECLARATION"]
192 192
  | SigDecl of { 
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : vhdl_cst_val_t option [@default None] 
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      init_val : vhdl_expr_t [@default IsNull]
196 196
    } [@name "SIGNAL_DECLARATION"]
197 197
  | Subprogram of {
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      name: vhdl_name_t [@default NoName]; 

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