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lustrec / src / tools / importer / vhdl_ast.ml @ d3f0059e

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let base_types = ["integer"; "character"; "bit"; "real"; "natural"; "positive"; "std_logic"; "std_logic_vector" ]
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(************************************************************************************)		   
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(*                     Constants                                                    *)
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(************************************************************************************)		   
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(* Std_logic values :
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    'U': uninitialized. This signal hasn't been set yet.
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    'X': unknown. Impossible to determine this value/result.
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    '0': logic 0
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    '1': logic 1
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    'Z': High Impedance
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    'W': Weak signal, can't tell if it should be 0 or 1.
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    'L': Weak signal that should probably go to 0
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    'H': Weak signal that should probably go to 1
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    '-': Don't care. *)			       
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let std_logic_cst = ["U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ]
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let literal_base = ["B"; "O"; "X"; "UB"; "UO"; "UX"; "SB"; "SO"; "SX"; "D"] (* Prefix of CstLiteral *)
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(* TODO: do we need more constructors ? *)
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type cst_val_t = 
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    CstInt of int 
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  | CstStdLogic of string
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  | CstLiteral of string [@name "CST_LITERAL"]
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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(*
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let pp_cst_val fmt c =
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  match c with
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  | CstInt i -> Format.fprintf fmt "%i" i
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  | CstStdLogic s -> if List.mem s std_logic_cst then Format.fprintf fmt "%s" s else assert false
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  | CstLiteral s -> Format.fprintf fmt "%s" s
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*)
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type vhdl_type_t =
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  | Base of string
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  | Range of string option * int * int
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  | Bit_vector of int * int
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  | Array of int * int * vhdl_type_t
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  | Enumerated of string list
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  | Void
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and vhdl_subtype_indication_t =
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  {
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    name : vhdl_name_t [@default NoName];
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    functionName : vhdl_name_t [@default NoName];
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    const: vhdl_constraint_t [@default NoConstraint];
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  }
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and vhdl_discrete_range_t =
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  | SubDiscreteRange of vhdl_subtype_indication_t [@name "SUB_DISCRETE_RANGE"]
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  | NamedRange of vhdl_name_t [@name "NAMED_RANGE"]
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  | DirectedRange of { direction: string; from: vhdl_expr_t; _to: vhdl_expr_t } [@name "RANGE_WITH_DIRECTION"]
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and vhdl_constraint_t =
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  | RefConstraint of { ref_name: vhdl_name_t; }
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  | RangeConstraint of { range: vhdl_discrete_range_t } [@name "RANGE_CONSTRAINT"]
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  | IndexConstraint of { ranges: vhdl_discrete_range_t list; } [@name "INDEX_CONSTRAINT"]
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  | ArrayConstraint of { ranges: vhdl_discrete_range_t list; sub: vhdl_constraint_t } [@name "ARRAY_CONSTRAINT"]
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  | RecordConstraint
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  | NoConstraint
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and vhdl_definition_t =
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  | Type of {name : vhdl_name_t ; definition: vhdl_type_t} [@name "TYPE_DECLARATION"]
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  | Subtype of {name : vhdl_name_t ; typ : vhdl_subtype_indication_t} [@name "SUBTYPE_DECLARATION"]
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and vhdl_expr_t =
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  | Call of vhdl_name_t [@name "CALL"]
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  | Cst of cst_val_t [@name "CONSTANT_VALUE"]
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  | Op of { id: string [@default ""]; args: vhdl_expr_t list [@default []]} [@name "EXPRESSION"]
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  | IsNull [@name "IsNull"]
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  | Time of { value: int; phy_unit: string [@default ""]}
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  | Sig of { name: vhdl_name_t; att: vhdl_signal_attributes_t option }
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  | SuffixMod of { expr : vhdl_expr_t; selection : vhdl_suffix_selection_t }
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  | Aggregate of { elems : vhdl_element_assoc_t list } [@name "AGGREGATE"]
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  | Others [@name "OTHERS"]
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and vhdl_name_t =
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  | Simple of string [@name "SIMPLE_NAME"]
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  | Identifier of string [@name "IDENTIFIER"]
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  | Selected of vhdl_name_t list [@name "SELECTED_NAME"]
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  | Index of { id: vhdl_name_t; exprs: vhdl_expr_t list } [@name "INDEXED_NAME"]
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  | Slice of { id: vhdl_name_t; range: vhdl_discrete_range_t } [@name "SLICE_NAME"]
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  | Attribute of { id: vhdl_name_t; designator: vhdl_name_t; expr: vhdl_expr_t [@default IsNull]} [@name "ATTRIBUTE_NAME"]
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  | Function of { id: vhdl_name_t; assoc_list: vhdl_assoc_element_t list } [@name "FUNCTION_CALL"]
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  | NoName
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and vhdl_assoc_element_t =
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  {
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    formal_name: vhdl_name_t option [@default Some NoName];
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    formal_arg: vhdl_name_t option [@default Some NoName];
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    actual_name: vhdl_name_t option [@default Some NoName];
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    actual_designator: vhdl_name_t option [@default Some NoName];
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    actual_expr: vhdl_expr_t option [@default Some IsNull];
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  }
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and vhdl_element_assoc_t =
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  {
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    choices: vhdl_expr_t list;
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    expr: vhdl_expr_t;
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  }
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and vhdl_array_attributes_t = 
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  | AAttInt of { id: string; arg: int; } 
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  | AAttAscending
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and vhdl_signal_attributes_t = SigAtt of string
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and vhdl_string_attributes_t = StringAtt of string
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and vhdl_suffix_selection_t = Idx of int | SuffixRange of int * int
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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(*
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let rec pp_vhdl_type fmt t =
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  match t with
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  | Base s -> Format.fprintf fmt "%s" s 
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  | Range(base, n, m) -> Format.fprintf fmt "%trange %i to %i" (fun fmt -> match base with Some s -> Format.fprintf fmt "%s " s | None -> ()) n m
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  | Bit_vector (n,m) -> Format.fprintf fmt "bit_vector(%i downto %i)" n m
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  | Array (n, m, base) -> Format.fprintf fmt "array (%i to %i) of %a" n m pp_vhdl_type base
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  | Enumerated sl -> Format.fprintf fmt "(%a)" (Utils.fprintf_list ~sep:", " Format.pp_print_string) sl
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  | Void -> Format.fprintf fmt ""
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*)
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(************************************************************************************)		   
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(*            Attributes for types, arrays, signals and strings                     *)
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(************************************************************************************)		   
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type 'basetype vhdl_type_attributes_t =
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  | TAttNoArg of { id: string }
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  | TAttIntArg of { id: string; arg: int }
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  | TAttValArg of { id: string; arg: 'basetype }
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  | TAttStringArg of { id: string; arg: string }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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let typ_att_noarg = ["base"; "left"; "right"; "high"; "low"]
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let typ_att_intarg = ["pos"; "val"; "succ"; "pred"; "leftof"; "rightof"]
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let typ_att_valarg = ["image"]
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let typ_att_stringarg = ["value"]
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let array_att_intarg = ["left"; "right"; "high"; "low"; "range"; "reverse_range"; "length"]  
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type vhdl_parameter_t =
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  {
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    names: vhdl_name_t list;
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    mode: string list [@default []];
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    typ: vhdl_subtype_indication_t;
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    init_val: cst_val_t option [@default Some (CstInt (0))];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_subprogram_spec_t =
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  {
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    name: string [@default ""];
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    typeMark: vhdl_name_t [@default NoName];
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    parameters: vhdl_parameter_t list;
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    isPure: bool [@default false];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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(************************************************************************************)		   
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(*                        Expressions  / Statements                                 *)
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(************************************************************************************)		   
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let arith_funs = ["+";"-";"*";"/";"mod"; "rem";"abs";"**";"&"]
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let bool_funs  = ["and"; "or"; "nand"; "nor"; "xor"; "not"]
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let rel_funs   = ["<";">";"<=";">=";"/=";"=";"?=";"?/=";"?<";"?<=";"?>";"?>=";"??"]
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let shift_funs = ["sll";"srl";"sla";"sra";"rol";"ror"]
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type vhdl_sequential_stmt_t = 
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  | VarAssign of { label: vhdl_name_t [@default NoName]; lhs: vhdl_name_t; rhs: vhdl_expr_t } [@name "VARIABLE_ASSIGNMENT_STATEMENT"]
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  | SigSeqAssign of { label: vhdl_name_t [@default NoName]; lhs: vhdl_name_t; rhs: vhdl_expr_t list} [@name "SIGNAL_ASSIGNMENT_STATEMENT"]
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  | If of { label: vhdl_name_t [@default NoName]; if_cases: vhdl_if_case_t list;
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    default: vhdl_sequential_stmt_t list [@default []]; } [@name "IF_STATEMENT"]
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  | Case of { label: vhdl_name_t [@default NoName]; guard: vhdl_expr_t; branches: vhdl_case_item_t list } [@name "CASE_STATEMENT_TREE"]
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  | Exit of { label: vhdl_name_t [@default NoName]; loop_label: string option [@default Some ""]; condition: vhdl_expr_t option [@default Some IsNull]} [@name "EXIT_STATEMENT"]
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  | Assert of { label: vhdl_name_t [@default NoName]; cond: vhdl_expr_t; report: vhdl_expr_t [@default IsNull]; severity: vhdl_expr_t [@default IsNull]} [@name "ASSERTION_STATEMENT"]
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  | Wait [@name "WAIT_STATEMENT"]
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  | Null of { label: vhdl_name_t [@default NoName]} [@name "NULL_STATEMENT"]
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  | Return of { label: vhdl_name_t [@default NoName]} [@name "RETURN_STATEMENT"]
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and vhdl_if_case_t = 
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  {
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    if_cond: vhdl_expr_t;
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    if_block: vhdl_sequential_stmt_t list;
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  }
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and vhdl_case_item_t = 
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  {
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    when_cond: vhdl_expr_t list;
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    when_stmt: vhdl_sequential_stmt_t list;
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_declaration_t =
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  | VarDecl of {
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : cst_val_t option [@default Some (CstInt (0))] 
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    } [@name "VARIABLE_DECLARATION"]
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  | CstDecl of { 
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : cst_val_t 
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    } [@name "CONSTANT_DECLARATION"]
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  | SigDecl of { 
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : cst_val_t option [@default Some (CstInt (0))] 
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    } [@name "SIGNAL_DECLARATION"]
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  | Subprogram of {
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      name: vhdl_name_t [@default NoName]; 
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      kind: string [@default ""]; 
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      spec: vhdl_subprogram_spec_t [@default {name="";typeMark=NoName;parameters=[];isPure=false}]; 
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      decl_part: vhdl_declaration_t list [@default []]; 
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      stmts: vhdl_sequential_stmt_t list [@default []]
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    } [@name "SUBPROGRAM_BODY"]
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_signal_condition_t =
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  {                            
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    expr: vhdl_expr_t list;              (* when expression *)
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    cond: vhdl_expr_t [@default IsNull];  (* optional else case expression. 
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                                             If None, could be a latch  *)
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_signal_selection_t =
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  {
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    expr : vhdl_expr_t;
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    when_sel: vhdl_expr_t list [@default []];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_conditional_signal_t =
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  {
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    postponed: bool [@default false];
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    label: vhdl_name_t [@default NoName];
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    lhs: vhdl_name_t;        (* assigned signal = target*)
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    rhs: vhdl_signal_condition_t list;                   (* expression *)
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    cond: vhdl_expr_t [@default IsNull];
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    delay: vhdl_expr_t [@default IsNull];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_process_t =
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  { 
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    id: vhdl_name_t [@default NoName];
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    declarations: vhdl_declaration_t list option [@key "PROCESS_DECLARATIVE_PART"] [@default Some []];
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    active_sigs: vhdl_name_t list [@default []];
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    body: vhdl_sequential_stmt_t list [@key "PROCESS_STATEMENT_PART"] [@default []]
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_selected_signal_t = 
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  { 
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    postponed: bool [@default false];
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    label: vhdl_name_t [@default NoName];
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    lhs: vhdl_name_t;      (* assigned signal = target *)
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    sel: vhdl_expr_t;  
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    branches: vhdl_signal_selection_t list [@default []];
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    delay: vhdl_expr_t option;
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_concurrent_stmt_t =
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  | SigAssign of vhdl_conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
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  | Process of vhdl_process_t [@name "PROCESS_STATEMENT"]
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  | SelectedSig of vhdl_selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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  (*
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type vhdl_statement_t =
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  (* | DeclarationStmt of declaration_stmt_t *)
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  | ConcurrentStmt of vhdl_concurrent_stmt_t
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  | SequentialStmt of vhdl_sequential_stmt_t
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   *)
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(************************************************************************************)		   
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(*                     Entities                                                     *)
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(************************************************************************************)		   
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type vhdl_port_mode_t = 
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    InPort     [@name "in"]
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  | OutPort    [@name "out"]
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  | InoutPort  [@name "inout"]
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  | BufferPort [@name "buffer"]
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[@@deriving show { with_path = false }, yojson];;
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type vhdl_port_t =
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  {
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    names: vhdl_name_t list [@default []];
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    mode: vhdl_port_mode_t [@default InPort];
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    typ: vhdl_subtype_indication_t;
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    expr: vhdl_expr_t [@default IsNull];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_entity_t =
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  {
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    name: vhdl_name_t [@default NoName];
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    generics: vhdl_port_t list [@default []];
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    ports: vhdl_port_t list [@default []];
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    declaration: vhdl_declaration_t list [@key "ENTITY_DECLARATIVE_PART"] [@default []];
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    stmts: vhdl_concurrent_stmt_t list [@key "ENTITY_STATEMENT_PART"] [@default []]; 
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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(************************************************************************************)		   
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(*                    Packages / Library loading                                    *)
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(************************************************************************************)		   
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(* Optional. Describes shared definitions *)
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type vhdl_package_t =
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  {
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    name: vhdl_name_t [@default NoName];
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    shared_defs: vhdl_definition_t list [@default []];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_load_t = 
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    Library of vhdl_name_t list [@name "LIBRARY_CLAUSE"] [@default []]
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  | Use of vhdl_name_t list [@name "USE_CLAUSE"] [@default []]
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[@@deriving show { with_path = false }, yojson];;
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(************************************************************************************)		   
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(*                        Architecture / VHDL Design                                *)
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(************************************************************************************)		   
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type vhdl_architecture_t =
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  {
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    name: vhdl_name_t [@default NoName];
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    entity: vhdl_name_t [@default NoName];
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    declarations: vhdl_declaration_t list [@key "ARCHITECTURE_DECLARATIVE_PART"] [@default []];
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    body: vhdl_concurrent_stmt_t list [@key "ARCHITECTURE_STATEMENT_PART"] [@default []]; 
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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(* TODO. Configuration is optional *)
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type vhdl_configuration_t = unit
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_library_unit_t = (* TODO: PACKAGE_BODY *)
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    Package of vhdl_package_t [@name "PACKAGE_DECLARATION"]
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  | Entities of vhdl_entity_t [@name "ENTITY_DECLARATION"]
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  | Architecture of vhdl_architecture_t [@name "ARCHITECTURE_BODY"]
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  | Configuration of vhdl_configuration_t [@name "CONFIGURATION_DECLARATION"]
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_design_unit_t =
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  {
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    contexts: vhdl_load_t list [@default []];
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    library: vhdl_library_unit_t;
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_design_file_t =
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  {
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    design_units: vhdl_design_unit_t list [@default []];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_file_t = 
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  {
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    design_file: vhdl_design_file_t [@default {design_units=[]}] [@key "DESIGN_FILE"];
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  }
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[@@deriving show { with_path = false }, yojson];;