Project

General

Profile

Revision d3f0059e src/tools/importer/vhdl_ast.ml

View differences:

src/tools/importer/vhdl_ast.ml
22 22
    CstInt of int 
23 23
  | CstStdLogic of string
24 24
  | CstLiteral of string [@name "CST_LITERAL"]
25
[@@deriving yojson {strict = false}];;
25
[@@deriving show { with_path = false }, yojson {strict = false}];;
26

  
27
(*
28
let pp_cst_val fmt c =
29
  match c with
30
  | CstInt i -> Format.fprintf fmt "%i" i
31
  | CstStdLogic s -> if List.mem s std_logic_cst then Format.fprintf fmt "%s" s else assert false
32
  | CstLiteral s -> Format.fprintf fmt "%s" s
33
*)
26 34

  
27 35
type vhdl_type_t =
28 36
  | Base of string
......
58 66
  | IsNull [@name "IsNull"]
59 67
  | Time of { value: int; phy_unit: string [@default ""]}
60 68
  | Sig of { name: vhdl_name_t; att: vhdl_signal_attributes_t option }
61
  | SuffixMod of { expr : vhdl_expr_t; selection : suffix_selection_t }
69
  | SuffixMod of { expr : vhdl_expr_t; selection : vhdl_suffix_selection_t }
62 70
  | Aggregate of { elems : vhdl_element_assoc_t list } [@name "AGGREGATE"]
63 71
  | Others [@name "OTHERS"]
64 72
and vhdl_name_t =
......
88 96
  | AAttAscending
89 97
and vhdl_signal_attributes_t = SigAtt of string
90 98
and vhdl_string_attributes_t = StringAtt of string
91
and suffix_selection_t = Idx of int | SuffixRange of int * int
92
[@@deriving yojson {strict = false}];;
99
and vhdl_suffix_selection_t = Idx of int | SuffixRange of int * int
100
[@@deriving show { with_path = false }, yojson {strict = false}];;
101

  
102
(*
103
let rec pp_vhdl_type fmt t =
104
  match t with
105
  | Base s -> Format.fprintf fmt "%s" s 
106
  | Range(base, n, m) -> Format.fprintf fmt "%trange %i to %i" (fun fmt -> match base with Some s -> Format.fprintf fmt "%s " s | None -> ()) n m
107
  | Bit_vector (n,m) -> Format.fprintf fmt "bit_vector(%i downto %i)" n m
108
  | Array (n, m, base) -> Format.fprintf fmt "array (%i to %i) of %a" n m pp_vhdl_type base
109
  | Enumerated sl -> Format.fprintf fmt "(%a)" (Utils.fprintf_list ~sep:", " Format.pp_print_string) sl
110
  | Void -> Format.fprintf fmt ""
111
*)
93 112

  
94 113
(************************************************************************************)		   
95 114
(*            Attributes for types, arrays, signals and strings                     *)
......
100 119
  | TAttIntArg of { id: string; arg: int }
101 120
  | TAttValArg of { id: string; arg: 'basetype }
102 121
  | TAttStringArg of { id: string; arg: string }
103
[@@deriving yojson {strict = false}];;
122
[@@deriving show { with_path = false }, yojson {strict = false}];;
104 123

  
105 124
let typ_att_noarg = ["base"; "left"; "right"; "high"; "low"]
106 125
let typ_att_intarg = ["pos"; "val"; "succ"; "pred"; "leftof"; "rightof"]
......
116 135
    typ: vhdl_subtype_indication_t;
117 136
    init_val: cst_val_t option [@default Some (CstInt (0))];
118 137
  }
119
[@@deriving yojson {strict = false}];;
138
[@@deriving show { with_path = false }, yojson {strict = false}];;
120 139

  
121 140
type vhdl_subprogram_spec_t =
122 141
  {
......
125 144
    parameters: vhdl_parameter_t list;
126 145
    isPure: bool [@default false];
127 146
  }
128
[@@deriving yojson {strict = false}];;
147
[@@deriving show { with_path = false }, yojson {strict = false}];;
129 148

  
130 149
(************************************************************************************)		   
131 150
(*                        Expressions  / Statements                                 *)
......
157 176
    when_cond: vhdl_expr_t list;
158 177
    when_stmt: vhdl_sequential_stmt_t list;
159 178
  }
160
[@@deriving yojson {strict = false}];;
179
[@@deriving show { with_path = false }, yojson {strict = false}];;
161 180

  
162 181
type vhdl_declaration_t =
163 182
  | VarDecl of {
......
182 201
      decl_part: vhdl_declaration_t list [@default []]; 
183 202
      stmts: vhdl_sequential_stmt_t list [@default []]
184 203
    } [@name "SUBPROGRAM_BODY"]
185
[@@deriving yojson {strict = false}];;
204
[@@deriving show { with_path = false }, yojson {strict = false}];;
186 205

  
187
type signal_condition_t =
206
type vhdl_signal_condition_t =
188 207
  {                            
189 208
    expr: vhdl_expr_t list;              (* when expression *)
190 209
    cond: vhdl_expr_t [@default IsNull];  (* optional else case expression. 
191 210
                                             If None, could be a latch  *)
192 211
  }
193
[@@deriving yojson {strict = false}];;
212
[@@deriving show { with_path = false }, yojson {strict = false}];;
194 213

  
195
type signal_selection_t =
214
type vhdl_signal_selection_t =
196 215
  {
197 216
    expr : vhdl_expr_t;
198 217
    when_sel: vhdl_expr_t list [@default []];
199 218
  }
200
[@@deriving yojson {strict = false}];;
219
[@@deriving show { with_path = false }, yojson {strict = false}];;
201 220

  
202
type conditional_signal_t =
221
type vhdl_conditional_signal_t =
203 222
  {
204 223
    postponed: bool [@default false];
205 224
    label: vhdl_name_t [@default NoName];
206 225
    lhs: vhdl_name_t;        (* assigned signal = target*)
207
    rhs: signal_condition_t list;                   (* expression *)
226
    rhs: vhdl_signal_condition_t list;                   (* expression *)
208 227
    cond: vhdl_expr_t [@default IsNull];
209 228
    delay: vhdl_expr_t [@default IsNull];
210 229
  }
211
[@@deriving yojson {strict = false}];;
230
[@@deriving show { with_path = false }, yojson {strict = false}];;
212 231

  
213
type process_t =
232
type vhdl_process_t =
214 233
  { 
215 234
    id: vhdl_name_t [@default NoName];
216 235
    declarations: vhdl_declaration_t list option [@key "PROCESS_DECLARATIVE_PART"] [@default Some []];
217 236
    active_sigs: vhdl_name_t list [@default []];
218 237
    body: vhdl_sequential_stmt_t list [@key "PROCESS_STATEMENT_PART"] [@default []]
219 238
  }
220
[@@deriving yojson {strict = false}];;
239
[@@deriving show { with_path = false }, yojson {strict = false}];;
221 240

  
222
type selected_signal_t = 
241
type vhdl_selected_signal_t = 
223 242
  { 
224 243
    postponed: bool [@default false];
225 244
    label: vhdl_name_t [@default NoName];
226 245
    lhs: vhdl_name_t;      (* assigned signal = target *)
227 246
    sel: vhdl_expr_t;  
228
    branches: signal_selection_t list [@default []];
247
    branches: vhdl_signal_selection_t list [@default []];
229 248
    delay: vhdl_expr_t option;
230 249
  }
231
[@@deriving yojson {strict = false}];;
250
[@@deriving show { with_path = false }, yojson {strict = false}];;
232 251
			   
233 252
type vhdl_concurrent_stmt_t =
234
  | SigAssign of conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
235
  | Process of process_t [@name "PROCESS_STATEMENT"]
236
  | SelectedSig of selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
237
[@@deriving yojson {strict = false}];;
253
  | SigAssign of vhdl_conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
254
  | Process of vhdl_process_t [@name "PROCESS_STATEMENT"]
255
  | SelectedSig of vhdl_selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
256
[@@deriving show { with_path = false }, yojson {strict = false}];;
238 257
  (*
239 258
type vhdl_statement_t =
240 259
  
......
252 271
  | OutPort    [@name "out"]
253 272
  | InoutPort  [@name "inout"]
254 273
  | BufferPort [@name "buffer"]
255
[@@deriving yojson];;
274
[@@deriving show { with_path = false }, yojson];;
256 275
	     
257 276
type vhdl_port_t =
258 277
  {
......
261 280
    typ: vhdl_subtype_indication_t;
262 281
    expr: vhdl_expr_t [@default IsNull];
263 282
  }
264
[@@deriving yojson {strict = false}];;
283
[@@deriving show { with_path = false }, yojson {strict = false}];;
265 284

  
266 285
type vhdl_entity_t =
267 286
  {
......
271 290
    declaration: vhdl_declaration_t list [@key "ENTITY_DECLARATIVE_PART"] [@default []];
272 291
    stmts: vhdl_concurrent_stmt_t list [@key "ENTITY_STATEMENT_PART"] [@default []]; 
273 292
  }
274
[@@deriving yojson {strict = false}];;
293
[@@deriving show { with_path = false }, yojson {strict = false}];;
275 294

  
276 295
(************************************************************************************)		   
277 296
(*                    Packages / Library loading                                    *)
......
283 302
    name: vhdl_name_t [@default NoName];
284 303
    shared_defs: vhdl_definition_t list [@default []];
285 304
  }
286
[@@deriving yojson {strict = false}];;
305
[@@deriving show { with_path = false }, yojson {strict = false}];;
287 306

  
288 307
type vhdl_load_t = 
289 308
    Library of vhdl_name_t list [@name "LIBRARY_CLAUSE"] [@default []]
290 309
  | Use of vhdl_name_t list [@name "USE_CLAUSE"] [@default []]
291
[@@deriving yojson];;
310
[@@deriving show { with_path = false }, yojson];;
292 311

  
293 312
(************************************************************************************)		   
294 313
(*                        Architecture / VHDL Design                                *)
......
301 320
    declarations: vhdl_declaration_t list [@key "ARCHITECTURE_DECLARATIVE_PART"] [@default []];
302 321
    body: vhdl_concurrent_stmt_t list [@key "ARCHITECTURE_STATEMENT_PART"] [@default []]; 
303 322
  }
304
[@@deriving yojson {strict = false}];;
323
[@@deriving show { with_path = false }, yojson {strict = false}];;
305 324
    
306 325
(* TODO. Configuration is optional *)
307 326
type vhdl_configuration_t = unit
308
[@@deriving yojson {strict = false}];;
327
[@@deriving show { with_path = false }, yojson {strict = false}];;
309 328

  
310 329
type vhdl_library_unit_t = (* TODO: PACKAGE_BODY *)
311 330
    Package of vhdl_package_t [@name "PACKAGE_DECLARATION"]
312 331
  | Entities of vhdl_entity_t [@name "ENTITY_DECLARATION"]
313 332
  | Architecture of vhdl_architecture_t [@name "ARCHITECTURE_BODY"]
314 333
  | Configuration of vhdl_configuration_t [@name "CONFIGURATION_DECLARATION"]
315
[@@deriving yojson {strict = false}];;
334
[@@deriving show { with_path = false }, yojson {strict = false}];;
316 335

  
317 336
type vhdl_design_unit_t =
318 337
  {
319 338
    contexts: vhdl_load_t list [@default []];
320 339
    library: vhdl_library_unit_t;
321 340
  }
322
[@@deriving yojson {strict = false}];;
341
[@@deriving show { with_path = false }, yojson {strict = false}];;
323 342

  
324 343
type vhdl_design_file_t =
325 344
  {
326 345
    design_units: vhdl_design_unit_t list [@default []];
327 346
  }
328
[@@deriving yojson {strict = false}];;
347
[@@deriving show { with_path = false }, yojson {strict = false}];;
329 348

  
330 349
type vhdl_file_t = 
331 350
  {
332 351
    design_file: vhdl_design_file_t [@default {design_units=[]}] [@key "DESIGN_FILE"];
333 352
  }
334
[@@deriving yojson];;
353
[@@deriving show { with_path = false }, yojson];;

Also available in: Unified diff