Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec / src / backends / VHDL / vhdl_ast.ml @ bd1f1929

History | View | Annotate | Download (16.7 KB)

1
let base_types = ["integer"; "character"; "bit"; "real"; "natural"; "positive"; "std_logic"; "std_logic_vector" ]
2
 
3
(************************************************************************************)		   
4
(*                     Constants                                                    *)
5
(************************************************************************************)		   
6

    
7
(* Std_logic values :
8
    'U': uninitialized. This signal hasn't been set yet.
9
    'X': unknown. Impossible to determine this value/result.
10
    '0': logic 0
11
    '1': logic 1
12
    'Z': High Impedance
13
    'W': Weak signal, can't tell if it should be 0 or 1.
14
    'L': Weak signal that should probably go to 0
15
    'H': Weak signal that should probably go to 1
16
    '-': Don't care. *)			       
17
let std_logic_cst = ["U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ]
18
let literal_base = ["B"; "O"; "X"; "UB"; "UO"; "UX"; "SB"; "SO"; "SX"; "D"] (* Prefix of CstLiteral *)
19

    
20
(* TODO: do we need more constructors ? *)
21
type vhdl_cst_val_t = 
22
    CstInt of int 
23
  | CstStdLogic of string
24
  | CstLiteral of string [@yojson.name "CST_LITERAL"]
25

    
26
(*
27
let pp_cst_val fmt c =
28
  match c with
29
  | CstInt i -> Format.fprintf fmt "%i" i
30
  | CstStdLogic s -> if List.mem s std_logic_cst then Format.fprintf fmt "%s" s else assert false
31
  | CstLiteral s -> Format.fprintf fmt "%s" s
32
*)
33

    
34
and vhdl_type_t =
35
  | Base of string
36
  | Range of string option * int * int
37
  | Bit_vector of int * int
38
  | Array of { indexes: vhdl_name_t list [@yojson.default []]; const: vhdl_constraint_t option [@yojson.default None]; definition: vhdl_subtype_indication_t } [@yojson.name "ARRAY_TYPE_DEFINITION"]
39
  | Record of vhdl_element_declaration_t list [@yojson.name "RECORD_TYPE_DEFINITION"]
40
  | Enumerated of vhdl_name_t list [@yojson.name "ENUMERATION_TYPE_DEFINITION"]
41
  | Void
42
and vhdl_element_declaration_t =
43
  { 
44
    ed_names : vhdl_name_t list [@yojson.key "names"];
45
    definition: vhdl_subtype_indication_t;
46
  }
47
and vhdl_subtype_indication_t =
48
  {
49
    si_name : vhdl_name_t [@yojson.default NoName] [@yojson.key "name"];
50
    functionName : vhdl_name_t [@yojson.default NoName];
51
    const: vhdl_constraint_t [@yojson.default NoConstraint];
52
  }
53
and vhdl_discrete_range_t =
54
  | SubDiscreteRange of vhdl_subtype_indication_t [@yojson.name "SUB_DISCRETE_RANGE"]
55
  | NamedRange of vhdl_name_t [@yojson.name "NAMED_RANGE"]
56
  | DirectedRange of { direction: string; from: vhdl_expr_t; _to: vhdl_expr_t } [@yojson.name "RANGE_WITH_DIRECTION"]
57
and vhdl_constraint_t =
58
  | RefConstraint of { ref_name: vhdl_name_t; }
59
  | RangeConstraint of { range: vhdl_discrete_range_t } [@yojson.name "RANGE_CONSTRAINT"]
60
  | IndexConstraint of { ranges: vhdl_discrete_range_t list; } [@yojson.name "INDEX_CONSTRAINT"]
61
  | ArrayConstraint of { ranges: vhdl_discrete_range_t list; sub: vhdl_constraint_t } [@yojson.name "ARRAY_CONSTRAINT"]
62
  | RecordConstraint
63
  | NoConstraint
64
and vhdl_definition_t =
65
  | Type of {name : vhdl_name_t ; definition: vhdl_type_t} [@yojson.name "TYPE_DECLARATION"]
66
  | Subtype of {name : vhdl_name_t ; typ : vhdl_subtype_indication_t} [@yojson.name "SUBTYPE_DECLARATION"]
67
and vhdl_expr_t =
68
  | Call of vhdl_name_t [@yojson.name "CALL"]
69
  | Cst of { value: vhdl_cst_val_t; unit_name: vhdl_name_t option [@yojson.default None]} [@yojson.name "CONSTANT_VALUE"]
70
  | Op of { id: string [@yojson.default ""]; args: vhdl_expr_t list [@yojson.default []]} [@yojson.name "EXPRESSION"]
71
  | IsNull [@yojson.name "IsNull"]
72
  | Time of { value: int; phy_unit: string [@yojson.default ""]}
73
  | Sig of { name: vhdl_name_t; att: vhdl_signal_attributes_t option [@yojson.default None]}
74
  | SuffixMod of { expr : vhdl_expr_t; selection : vhdl_suffix_selection_t }
75
  | Aggregate of { elems : vhdl_element_assoc_t list [@yojson.default []]} [@yojson.name "AGGREGATE"]
76
  | QualifiedExpression of { type_mark : vhdl_name_t; aggregate : vhdl_element_assoc_t list [@yojson.default []]; expression : vhdl_expr_t option [@yojson.default None]} [@yojson.name "QUALIFIED_EXPRESSION"]
77
  | Others [@yojson.name "OTHERS"]
78
and vhdl_name_t = (* Add something like TOKEN_NAME for specific keywords (open, all, ...) ? *)
79
  | Simple of string [@yojson.name "SIMPLE_NAME"]
80
  | Identifier of string [@yojson.name "IDENTIFIER"]
81
  | Selected of vhdl_name_t list [@yojson.name "SELECTED_NAME"]
82
  | Index of { id: vhdl_name_t; exprs: vhdl_expr_t list } [@yojson.name "INDEXED_NAME"]
83
  | Slice of { id: vhdl_name_t; range: vhdl_discrete_range_t } [@yojson.name "SLICE_NAME"]
84
  | Attribute of { id: vhdl_name_t; designator: vhdl_name_t; expr: vhdl_expr_t [@yojson.default IsNull]} [@yojson.name "ATTRIBUTE_NAME"]
85
  | Function of { id: vhdl_name_t; assoc_list: vhdl_assoc_element_t list } [@yojson.name "FUNCTION_CALL"]
86
  | Open [@yojson.name "OPEN"]
87
  | NoName
88
and vhdl_assoc_element_t =
89
  {
90
    formal_name: vhdl_name_t option [@yojson.default None];
91
    formal_arg: vhdl_name_t option [@yojson.default None];
92
    actual_name: vhdl_name_t option [@yojson.default None];
93
    actual_designator: vhdl_name_t option [@yojson.default None];
94
    actual_expr: vhdl_expr_t option [@yojson.default None];
95
  }
96
and vhdl_element_assoc_t =
97
  {
98
    choices: vhdl_expr_t list [@yojson.default []];
99
    expr: vhdl_expr_t;
100
  }
101
and vhdl_array_attributes_t = 
102
  | AAttInt of { id: string; arg: int; } 
103
  | AAttAscending
104
and vhdl_signal_attributes_t = SigAtt of string
105
and vhdl_string_attributes_t = StringAtt of string
106
and vhdl_suffix_selection_t = Idx of int | SuffixRange of int * int
107

    
108
(*
109
let rec pp_vhdl_type fmt t =
110
  match t with
111
  | Base s -> Format.fprintf fmt "%s" s 
112
  | Range(base, n, m) -> Format.fprintf fmt "%trange %i to %i" (fun fmt -> match base with Some s -> Format.fprintf fmt "%s " s | None -> ()) n m
113
  | Bit_vector (n,m) -> Format.fprintf fmt "bit_vector(%i downto %i)" n m
114
  | Array (n, m, base) -> Format.fprintf fmt "array (%i to %i) of %a" n m pp_vhdl_type base
115
  | Enumerated sl -> Format.fprintf fmt "(%a)" (Utils.fprintf_list ~sep:", " Format.pp_print_string) sl
116
  | Void -> Format.fprintf fmt ""
117
*)
118

    
119
(************************************************************************************)		   
120
(*            Attributes for types, arrays, signals and strings                     *)
121
(************************************************************************************)		   
122

    
123
(*and 'basetype vhdl_type_attributes_t =
124
  | TAttNoArg of { id: string }
125
  | TAttIntArg of { id: string; arg: int }
126
  | TAttValArg of { id: string; arg: 'basetype }
127
  | TAttStringArg of { id: string; arg: string } *)
128

    
129
and vhdl_parameter_t =
130
  {
131
    parameter_names: vhdl_name_t list [@yojson.key "names"];
132
    parameter_mode: string list [@yojson.default []] [@yojson.key "mode"];
133
    parameter_typ: vhdl_subtype_indication_t [@yojson.key "typ"];
134
    init_val: vhdl_cst_val_t option [@yojson.default None];
135
  }
136

    
137
and vhdl_subprogram_spec_t =
138
  {
139
    ss_name: string [@yojson.default ""] [@yojson.key "name"];
140
    subprogram_type: string [@yojson.default ""];
141
    typeMark: vhdl_name_t [@yojson.default NoName];
142
    parameters: vhdl_parameter_t list [@yojson.default []];
143
    isPure: bool [@yojson.default false];
144
  }
145

    
146
(************************************************************************************)		   
147
(*                        Expressions  / Statements                                 *)
148
(************************************************************************************)		   
149

    
150
and vhdl_waveform_element_t =
151
  {
152
    value: vhdl_expr_t option [@yojson.default None];
153
    we_delay: vhdl_expr_t option [@yojson.default None] [@yojson.key "delay"];
154
  }
155

    
156
and vhdl_sequential_stmt_t = 
157
  | VarAssign of { label: vhdl_name_t option [@yojson.default None]; seqs_lhs: vhdl_name_t [@yojson.key "lhs"]; rhs: vhdl_expr_t } [@yojson.name "VARIABLE_ASSIGNMENT_STATEMENT"]
158
  | SigSeqAssign of { label: vhdl_name_t option [@yojson.default None]; seqs_lhs: vhdl_name_t [@yojson.key "lhs"]; rhs: vhdl_waveform_element_t list} [@yojson.name "SIGNAL_ASSIGNMENT_STATEMENT"]
159
  | If of { label: vhdl_name_t option [@yojson.default None]; if_cases: vhdl_if_case_t list;
160
    default: vhdl_sequential_stmt_t list [@yojson.default []]; } [@yojson.name "IF_STATEMENT"]
161
  | Case of { label: vhdl_name_t option [@yojson.default None]; guard: vhdl_expr_t; branches: vhdl_case_item_t list } [@yojson.name "CASE_STATEMENT_TREE"]
162
  | Exit of { label: vhdl_name_t option [@yojson.default None]; loop_label: string option [@yojson.default Some ""]; condition: vhdl_expr_t option [@yojson.default Some IsNull]} [@yojson.name "EXIT_STATEMENT"]
163
  | Assert of { label: vhdl_name_t option [@yojson.default None]; cond: vhdl_expr_t; report: vhdl_expr_t [@yojson.default IsNull]; severity: vhdl_expr_t [@yojson.default IsNull]} [@yojson.name "ASSERTION_STATEMENT"]
164
  | ProcedureCall of { label: vhdl_name_t option [@yojson.default None]; name: vhdl_name_t; assocs: vhdl_assoc_element_t list [@yojson.default []] } [@yojson.name "PROCEDURE_CALL_STATEMENT"]
165
  | Wait of { sensitivity: vhdl_name_t list [@yojson.default []] } [@yojson.name "WAIT_STATEMENT"]
166
  | Null of { label: vhdl_name_t option [@yojson.default None]} [@yojson.name "NULL_STATEMENT"]
167
  | Return of { label: vhdl_name_t option [@yojson.default None]; expr: vhdl_expr_t option [@yojson.default None]} [@yojson.name "RETURN_STATEMENT"]
168
and vhdl_if_case_t = 
169
  {
170
    if_cond: vhdl_expr_t;
171
    if_block: vhdl_sequential_stmt_t list;
172
  }
173
and vhdl_case_item_t = 
174
  {
175
    when_cond: vhdl_expr_t list;
176
    when_stmt: vhdl_sequential_stmt_t list;
177
  }
178

    
179
and vhdl_port_mode_t = 
180
    InPort     [@yojson.name "in"]
181
  | OutPort    [@yojson.name "out"]
182
  | InoutPort  [@yojson.name "inout"]
183
  | BufferPort [@yojson.name "buffer"]
184
	     
185
and vhdl_port_t =
186
  {
187
    port_names: vhdl_name_t list [@yojson.default []] [@yojson.key "names"];
188
    port_mode: vhdl_port_mode_t [@yojson.default InPort] [@yojson.key "mode"];
189
    port_typ: vhdl_subtype_indication_t [@yojson.key "typ"];
190
    port_expr: vhdl_expr_t [@yojson.default IsNull] [@yojson.key "expr"];
191
  }
192

    
193
and vhdl_declaration_t =
194
  | VarDecl of {
195
      names : vhdl_name_t list; 
196
      typ : vhdl_subtype_indication_t; 
197
      init_val : vhdl_expr_t [@yojson.default IsNull] 
198
    } [@yojson.name "VARIABLE_DECLARATION"]
199
  | CstDecl of { 
200
      names : vhdl_name_t list; 
201
      typ : vhdl_subtype_indication_t; 
202
      init_val : vhdl_expr_t
203
    } [@yojson.name "CONSTANT_DECLARATION"]
204
  | SigDecl of { 
205
      names : vhdl_name_t list; 
206
      typ : vhdl_subtype_indication_t; 
207
      init_val : vhdl_expr_t [@yojson.default IsNull]
208
    } [@yojson.name "SIGNAL_DECLARATION"]
209
  | ComponentDecl of {
210
      name: vhdl_name_t [@yojson.default NoName];
211
      generics: vhdl_port_t list [@yojson.default []];
212
      ports: vhdl_port_t list [@yojson.default []];
213
    } [@yojson.name "COMPONENT_DECLARATION"]
214
  | Subprogram of {
215
      spec: vhdl_subprogram_spec_t; 
216
      decl_part: vhdl_declaration_t list [@yojson.default []]; 
217
      stmts: vhdl_sequential_stmt_t list [@yojson.default []]
218
    } [@yojson.name "SUBPROGRAM_BODY"]
219

    
220
and vhdl_load_t = 
221
    Library of vhdl_name_t list [@yojson.name "LIBRARY_CLAUSE"] [@yojson.default []]
222
  | Use of vhdl_name_t list [@yojson.name "USE_CLAUSE"] [@yojson.default []]
223

    
224
and vhdl_declarative_item_t =
225
  {
226
    use_clause: vhdl_load_t option [@yojson.default None];
227
    di_declaration: vhdl_declaration_t option [@yojson.default None] [@yojson.key "declaration"];
228
    di_definition: vhdl_definition_t option [@yojson.default None] [@yojson.key "definition"];
229
  }
230

    
231
and vhdl_signal_condition_t =
232
  {                            
233
    sc_expr: vhdl_waveform_element_t list [@yojson.default []] [@yojson.key "expr"];              (* when expression *)
234
    cond: vhdl_expr_t option [@yojson.default None];  (* optional else case expression. 
235
                                             If None, could be a latch  *)
236
  }
237

    
238
and vhdl_signal_selection_t =
239
  {
240
    ss_expr : vhdl_waveform_element_t list [@yojson.default []] [@yojson.key "expr"];
241
    when_sel: vhdl_expr_t list [@yojson.default []];
242
  }
243

    
244
and vhdl_conditional_signal_t =
245
  {
246
    cs_postponed: bool [@yojson.default false] [@yojson.key "postponed"];
247
    cs_label: vhdl_name_t option [@yojson.default None] [@yojson.key "label"];
248
    cs_lhs: vhdl_name_t [@yojson.key "lhs"];        (* assigned signal = target*)
249
    rhs: vhdl_signal_condition_t list;                   (* expression *)
250
    cs_delay: vhdl_expr_t [@yojson.default IsNull] [@yojson.key "delay"];
251
  }
252

    
253
and vhdl_process_t =
254
  { 
255
    id: vhdl_name_t [@yojson.default NoName];
256
    p_declarations: vhdl_declarative_item_t list [@yojson.key "PROCESS_DECLARATIVE_PART"] [@yojson.default []];
257
    active_sigs: vhdl_name_t list [@yojson.default []];
258
    p_body: vhdl_sequential_stmt_t list [@yojson.key "PROCESS_STATEMENT_PART"] [@yojson.default []]
259
  }
260

    
261
and vhdl_selected_signal_t = 
262
  { 
263
    ss_postponed: bool [@yojson.default false] [@yojson.key "postponed"];
264
    ss_label: vhdl_name_t option [@yojson.default None] [@yojson.key "label"];
265
    ss_lhs: vhdl_name_t [@yojson.key "lhs"];      (* assigned signal = target *)
266
    sel: vhdl_expr_t;
267
    branches: vhdl_signal_selection_t list [@yojson.default []];
268
    ss_delay: vhdl_expr_t option [@yojson.default None] [@yojson.key "delay"];
269
  }
270

    
271
and vhdl_component_instantiation_t =
272
  {
273
    ci_name: vhdl_name_t [@yojson.key "name"];
274
    inst_unit: vhdl_name_t;
275
    inst_unit_type : string [@yojson.default ""];
276
    archi_name: vhdl_name_t option [@yojson.default None];
277
    generic_map: vhdl_assoc_element_t list [@yojson.default []];
278
    port_map: vhdl_assoc_element_t list [@yojson.default []];
279
  }
280

    
281
and vhdl_concurrent_stmt_t =
282
  | SigAssign of vhdl_conditional_signal_t [@yojson.name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
283
  | Process of vhdl_process_t [@yojson.name "PROCESS_STATEMENT"]
284
  | SelectedSig of vhdl_selected_signal_t [@yojson.name "SELECTED_SIGNAL_ASSIGNMENT"]
285
  | ComponentInst of vhdl_component_instantiation_t [@yojson.name "COMPONENT_INSTANTIATION_STATEMENT"]
286
  (*
287
type vhdl_statement_t =
288
  
289
  (* | DeclarationStmt of declaration_stmt_t *)
290
  | ConcurrentStmt of vhdl_concurrent_stmt_t
291
  | SequentialStmt of vhdl_sequential_stmt_t
292
   *)
293
		     
294
(************************************************************************************)		   
295
(*                     Entities                                                     *)
296
(************************************************************************************)
297

    
298
and vhdl_entity_t =
299
  {
300
    e_name: vhdl_name_t [@yojson.default NoName] [@yojson.key "name"];
301
    generics: vhdl_port_t list [@yojson.default []];
302
    ports: vhdl_port_t list [@yojson.default []];
303
    e_declaration: vhdl_declarative_item_t list [@yojson.key "ENTITY_DECLARATIVE_PART"] [@yojson.default []];
304
    stmts: vhdl_concurrent_stmt_t list [@yojson.key "ENTITY_STATEMENT_PART"] [@yojson.default []]; 
305
  }
306

    
307
(************************************************************************************)		   
308
(*                    Packages / Library loading                                    *)
309
(************************************************************************************)		   
310
				
311
(* Optional. Describes shared definitions *)
312
and vhdl_package_t =
313
  {
314
    p_name: vhdl_name_t [@yojson.default NoName] [@yojson.key "name"];
315
    shared_defs: vhdl_definition_t list [@yojson.default []];
316
    shared_decls: vhdl_declaration_t list [@yojson.default []];
317
    shared_uses: vhdl_load_t list [@yojson.default []];
318
  }
319

    
320
(************************************************************************************)		   
321
(*                        Architecture / VHDL Design                                *)
322
(************************************************************************************)		   
323
				       
324
and vhdl_architecture_t =
325
  {
326
    a_name: vhdl_name_t [@yojson.default NoName] [@yojson.key "name"];
327
    entity: vhdl_name_t [@yojson.default NoName];
328
    a_declarations: vhdl_declarative_item_t list [@yojson.key "ARCHITECTURE_DECLARATIVE_PART"] [@yojson.default []];
329
    a_body: vhdl_concurrent_stmt_t list [@yojson.key "ARCHITECTURE_STATEMENT_PART"] [@yojson.default []]; 
330
  }
331
    
332
(* TODO. Configuration is optional *)
333
and vhdl_configuration_t = unit
334

    
335
and vhdl_library_unit_t = (* TODO: PACKAGE_BODY *)
336
    Package of vhdl_package_t [@yojson.name "PACKAGE_DECLARATION"]
337
  | Entities of vhdl_entity_t [@yojson.name "ENTITY_DECLARATION"]
338
  | Architecture of vhdl_architecture_t [@yojson.name "ARCHITECTURE_BODY"]
339
  | Configuration of vhdl_configuration_t [@yojson.name "CONFIGURATION_DECLARATION"]
340

    
341
and vhdl_design_unit_t =
342
  {
343
    contexts: vhdl_load_t list [@yojson.default []];
344
    library: vhdl_library_unit_t;
345
  }
346

    
347
and vhdl_design_file_t =
348
  {
349
    design_units: vhdl_design_unit_t list [@yojson.default []];
350
  }
351

    
352
and vhdl_file_t = 
353
  {
354
    design_file: vhdl_design_file_t [@yojson.default {design_units=[]}] [@yojson.key "DESIGN_FILE"];
355
  }
356
(*[@@deriving show { with_path = false }]*)
357
[@@deriving visitors { variety = "iter"; name = "vhdl_iter"; polymorphic = true }, 
358
            visitors { variety = "map"; name = "vhdl_map"; polymorphic = true },
359
            yojson];;