Project

General

Profile

Revision 8f9ce6d4 src/backends/VHDL/vhdl_test.ml

View differences:

src/backends/VHDL/vhdl_test.ml
32 32
			    Process {
33 33
				id = None;
34 34
				active_sigs = ["clk"; "rst"];
35
				body = [];
35
				body = [
36
				    
37
				  ];
36 38
			      };
37 39
			    SigAssign {
38 40
				lhs = "q";

Also available in: Unified diff