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lustrec / src / backends / VHDL / vhdl_test.ml @ 8f9ce6d4

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open Vhdl_ast
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let design1 = {
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    packages = [{name = "typedef"; shared_defs = [Subtype{name = "byte"; definition = Bit_vector (7, 0)}]}];
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    libraries = [Use ["work";"typedef";"all"]];
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    entities = [{ name = "data_path";
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		  generics = [];
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		  ports = [
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		      {name = "clk"; kind = InPort; typ = Base "boolean"};
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		      {name = "rst"; kind = InPort; typ = Base "boolean"};
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		      {name = "s_1"; kind = InPort; typ = Base "boolean"};
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		      {name = "s0"; kind = InPort; typ = Base "bit"};
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		      {name = "s1"; kind = InPort; typ = Base "bit"};
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		      {name = "d0"; kind = InPort; typ = Base "byte"};
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		      {name = "d1"; kind = InPort; typ = Base "byte"};
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		      {name = "d2"; kind = InPort; typ = Base "byte"};
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		      {name = "d3"; kind = InPort; typ = Base "byte"};
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		      {name = "q"; kind = OutPort; typ = Base "byte"};
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		    ];
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		}];
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    architectures = [{
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			name = "behavior";
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			entity = "data_path";
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			declarations = [
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			    SigDecl { name = "reg"; typ = Base "byte"; init_val = None};
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			    SigDecl { name = "shft"; typ = Base "byte"; init_val = None};
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			    SigDecl { name = "sel"; typ = Bit_vector(1,0); init_val = None};
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			  ];
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			body = [
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			    Process {
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				id = None;
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				active_sigs = ["clk"; "rst"];
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				body = [
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				  ];
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			      };
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			    SigAssign {
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				lhs = "q";
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				rhs = Var "shft";
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				cond = None;
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			      }
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			  ];
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		      }];
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    configuration = None;
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  }
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