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Revision 6f9095f6 src/backends/VHDL/vhdl_ast_deriving.ml

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src/backends/VHDL/vhdl_ast_deriving.ml
4751 4751
  {
4752 4752
  name: vhdl_name_t ;
4753 4753
  inst_unit: vhdl_name_t ;
4754
  archi_name: vhdl_name_t option [@default None];
4754 4755
  generic_map: vhdl_assoc_element_t option [@default None];
4755 4756
  port_map: vhdl_assoc_element_t option [@default None]}[@@deriving
4756 4757
                                                          ((show
......
4763 4764
                                                                 strict =
4764 4765
                                                                   false
4765 4766
                                                               }))]
4767

  
4766 4768
(* TODO *)
4767 4769
let rec pp_vhdl_component_instantiation_t :
4768 4770
  Format.formatter ->
4769 4771
    vhdl_component_instantiation_t -> Ppx_deriving_runtime.unit
4770 4772
  =
4771
  let __3 () = pp_vhdl_assoc_element_t
4773
  let __4 () = pp_vhdl_assoc_element_t
4774
  
4775
  and __3 () = pp_vhdl_assoc_element_t
4772 4776
  
4773
  and __2 () = pp_vhdl_assoc_element_t
4777
  and __2 () = pp_vhdl_name_t
4774 4778
  
4775 4779
  and __1 () = pp_vhdl_name_t
4776 4780
  
......
4779 4783
  ((let open! Ppx_deriving_runtime in
4780 4784
      fun fmt  ->
4781 4785
        fun x  ->
4782
          Format.fprintf fmt "@[<2>{ ";
4783
          ((((Format.fprintf fmt "@[%s =@ " "name";
4784
              ((__0 ()) fmt) x.name;
4785
              Format.fprintf fmt "@]");
4786
             Format.fprintf fmt ";@ ";
4787
             Format.fprintf fmt "@[%s =@ " "inst_unit";
4788
             ((__1 ()) fmt) x.inst_unit;
4789
             Format.fprintf fmt "@]");
4790
            Format.fprintf fmt ";@ ";
4791
            Format.fprintf fmt "@[%s =@ " "generic_map";
4792
            ((function
4793
              | None  -> Format.pp_print_string fmt "None"
4794
              | Some x ->
4795
                  (Format.pp_print_string fmt "(Some ";
4796
                   ((__2 ()) fmt) x;
4797
                   Format.pp_print_string fmt ")"))) x.generic_map;
4798
            Format.fprintf fmt "@]");
4799
           Format.fprintf fmt ";@ ";
4800
           Format.fprintf fmt "@[%s =@ " "port_map";
4801
           ((function
4786
          ((__0 ()) fmt) x.name;
4787
          Format.fprintf fmt " : ";
4788
          ((__1 ()) fmt) x.inst_unit;
4789
          ((function
4790
             | None  -> Format.pp_print_string fmt ""
4791
             | Some x ->
4792
                 (Format.pp_print_string fmt "(";
4793
                 ((__2 ()) fmt) x;
4794
                 Format.pp_print_string fmt ")@;"))) x.archi_name;
4795
          ((function
4796
             | None  -> Format.pp_print_string fmt ""
4797
             | Some x ->
4798
                 (Format.pp_print_string fmt "(";
4799
                 ((__3 ()) fmt) x;
4800
                 Format.pp_print_string fmt ")@;"))) x.generic_map;
4801
          ((function
4802 4802
             | None  -> Format.pp_print_string fmt "None"
4803 4803
             | Some x ->
4804
                 (Format.pp_print_string fmt "(Some ";
4805
                  ((__3 ()) fmt) x;
4806
                  Format.pp_print_string fmt ")"))) x.port_map;
4807
           Format.fprintf fmt "@]");
4808
          Format.fprintf fmt "@ }@]")
4804
                 (Format.pp_print_string fmt "(";
4805
                 ((__4 ()) fmt) x;
4806
                 Format.pp_print_string fmt ")@;"))) x.port_map;)
4809 4807
    [@ocaml.warning "-A"])
4810 4808

  
4811 4809
and show_vhdl_component_instantiation_t :
......
4841 4839
            :: fields
4842 4840
           in
4843 4841
        let fields =
4842
          if x.archi_name = None
4843
          then fields
4844
          else
4845
            ("archi_name",
4846
              (((function
4847
                 | None  -> `Null
4848
                 | Some x -> ((fun x  -> vhdl_name_t_to_yojson x)) x))
4849
                 x.archi_name))
4850
            :: fields
4851
           in
4852
        let fields =
4844 4853
          ("inst_unit", ((fun x  -> vhdl_name_t_to_yojson x) x.inst_unit)) ::
4845 4854
          fields  in
4846 4855
        let fields = ("name", ((fun x  -> vhdl_name_t_to_yojson x) x.name))
......
4855 4864
  ((let open! Ppx_deriving_yojson_runtime in
4856 4865
      function
4857 4866
      | `Assoc xs ->
4858
          let rec loop xs ((arg0,arg1,arg2,arg3) as _state) =
4867
          let rec loop xs ((arg0,arg1,arg2,arg3,arg4) as _state) =
4859 4868
            match xs with
4860 4869
            | ("name",x)::xs ->
4861 4870
                loop xs
4862
                  (((fun x  -> vhdl_name_t_of_yojson x) x), arg1, arg2, arg3)
4871
                  (((fun x  -> vhdl_name_t_of_yojson x) x), arg1, arg2, arg3,
4872
                    arg4)
4863 4873
            | ("inst_unit",x)::xs ->
4864 4874
                loop xs
4865
                  (arg0, ((fun x  -> vhdl_name_t_of_yojson x) x), arg2, arg3)
4866
            | ("generic_map",x)::xs ->
4875
                  (arg0, ((fun x  -> vhdl_name_t_of_yojson x) x), arg2, arg3,
4876
                    arg4)
4877
            | ("archi_name",x)::xs ->
4867 4878
                loop xs
4868 4879
                  (arg0, arg1,
4869 4880
                    ((function
4870 4881
                      | `Null -> Result.Ok None
4871 4882
                      | x ->
4883
                          ((fun x  -> vhdl_name_t_of_yojson x) x) >>=
4884
                            ((fun x  -> Result.Ok (Some x)))) x), arg3, arg4)
4885
            | ("generic_map",x)::xs ->
4886
                loop xs
4887
                  (arg0, arg1, arg2,
4888
                    ((function
4889
                      | `Null -> Result.Ok None
4890
                      | x ->
4872 4891
                          ((fun x  -> vhdl_assoc_element_t_of_yojson x) x)
4873
                            >>= ((fun x  -> Result.Ok (Some x)))) x), arg3)
4892
                            >>= ((fun x  -> Result.Ok (Some x)))) x), arg4)
4874 4893
            | ("port_map",x)::xs ->
4875 4894
                loop xs
4876
                  (arg0, arg1, arg2,
4895
                  (arg0, arg1, arg2, arg3,
4877 4896
                    ((function
4878 4897
                      | `Null -> Result.Ok None
4879 4898
                      | x ->
4880 4899
                          ((fun x  -> vhdl_assoc_element_t_of_yojson x) x)
4881 4900
                            >>= ((fun x  -> Result.Ok (Some x)))) x))
4882 4901
            | [] ->
4883
                arg3 >>=
4884
                  ((fun arg3  ->
4885
                      arg2 >>=
4886
                        (fun arg2  ->
4887
                           arg1 >>=
4888
                             (fun arg1  ->
4889
                                arg0 >>=
4890
                                  (fun arg0  ->
4891
                                     Result.Ok
4892
                                       {
4893
                                         name = arg0;
4894
                                         inst_unit = arg1;
4895
                                         generic_map = arg2;
4896
                                         port_map = arg3
4897
                                       })))))
4902
                arg4 >>=
4903
                  ((fun arg4  ->
4904
                      arg3 >>=
4905
                        (fun arg3  ->
4906
                           arg2 >>=
4907
                             (fun arg2  ->
4908
                                arg1 >>=
4909
                                  (fun arg1  ->
4910
                                     arg0 >>=
4911
                                       (fun arg0  ->
4912
                                          Result.Ok
4913
                                            {
4914
                                              name = arg0;
4915
                                              inst_unit = arg1;
4916
                                              archi_name = arg2;
4917
                                              generic_map = arg3;
4918
                                              port_map = arg4
4919
                                            }))))))
4898 4920
            | _::xs -> loop xs _state  in
4899 4921
          loop xs
4900 4922
            ((Result.Error "Vhdl_ast.vhdl_component_instantiation_t.name"),
4901 4923
              (Result.Error
4902 4924
                 "Vhdl_ast.vhdl_component_instantiation_t.inst_unit"),
4903
              (Result.Ok None), (Result.Ok None))
4925
              (Result.Ok None), (Result.Ok None), (Result.Ok None))
4904 4926
      | _ -> Result.Error "Vhdl_ast.vhdl_component_instantiation_t")
4905 4927
  [@ocaml.warning "-A"])
4928

  
4906 4929
type vhdl_concurrent_stmt_t =
4907 4930
  | SigAssign of vhdl_conditional_signal_t
4908 4931
  [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]

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