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lustrec / src / backends / VHDL / vhdl_test.ml @ 684d39e7

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open Vhdl_ast
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let design1 = {
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    packages = [{name = "typedef"; shared_defs = [Subtype{name = "byte"; definition = Bit_vector (7, 0)}]}];
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    libraries = [Use ["work";"typedef";"all"]];
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    entities = [{ name = "data_path";
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		  generics = [];
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		  ports = [
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		      {name = "clk"; kind = InPort; typ = Base "boolean"};
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		      {name = "rst"; kind = InPort; typ = Base "boolean"};
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		      {name = "s_1"; kind = InPort; typ = Base "boolean"};
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		      {name = "s0"; kind = InPort; typ = Base "bit"};
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		      {name = "s1"; kind = InPort; typ = Base "bit"};
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		      {name = "d0"; kind = InPort; typ = Base "byte"};
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		      {name = "d1"; kind = InPort; typ = Base "byte"};
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		      {name = "d2"; kind = InPort; typ = Base "byte"};
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		      {name = "d3"; kind = InPort; typ = Base "byte"};
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		      {name = "q"; kind = OutPort; typ = Base "byte"};
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		    ];
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		}];
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    architectures = [{
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			name = "behavior";
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			entity = "data_path";
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			declarations = [
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			    SigDecl { name = "reg"; typ = Base "byte"; init_val = None};
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			    SigDecl { name = "shft"; typ = Base "byte"; init_val = None};
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			    SigDecl { name = "sel"; typ = Bit_vector(1,0); init_val = None};
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			  ];
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			body = [
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			    Process {
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				id = None;
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				active_sigs = ["clk"; "rst"];
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				body = [
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				    If {
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					if_cases = [
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					  {
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					    if_cond = Sig{ name = "rst"; att = None };
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					    if_block = [
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						SigSeqAssign { lhs = "req"; rhs = Cst (CstBV("x", "00"))};
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						SigSeqAssign { lhs = "shft"; rhs = Cst (CstBV("x", "00"))};
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					      ];
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					  };
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					  {
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					    if_cond = Op {id = "and"; args = [Sig{ name = "clk"; att = None };
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									      Sig{ name = "clk"; att = Some (SigAtt "event") }]};
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					    if_block = [
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						SigSeqAssign { lhs = "req"; rhs = Op { id = "&"; args = [
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											   Sig{ name = "s0"; att = None };
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											   Sig{ name = "s1"; att = None }
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											 ]
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										     }
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							     };
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						Case {
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						    guard = Sig{ name = "sel"; att = None };
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						    branches = [
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							{
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							  when_cond = Cst (CstBV("b", "00"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d0"; att = None }};
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							};
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							{
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							  when_cond = Cst (CstBV("b", "10"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d1"; att = None }};
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							};
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							{
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							  when_cond = Cst (CstBV("b", "01"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d2"; att = None }};
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							};
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							{
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							  when_cond = Cst (CstBV("b", "11"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d3"; att = None }};
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							};
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						      ]
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						  };
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						If {
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						    if_cases = [
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						      {
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							if_cond = Sig{ name = "s_1"; att = None };
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							if_block = [
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							    SigSeqAssign {
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								lhs = "shft";
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								rhs = Op { id = "&";
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									   args = [
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									       SuffixMod {
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										   expr = Sig{ name = "shft"; att = None };
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										   selection = Range (6,0);
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										 };
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									       SuffixMod {
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										   expr = Sig{ name = "shft"; att = None };
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										   selection = Idx 7;
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										 }
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									     ]
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									 }
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							      };
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							  ];
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						      };
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						    ];
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						    default = Some [
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								  SigSeqAssign { lhs = "shft"; rhs = Var "reg"};
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								]
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						  };
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					      ];
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					  };
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					];
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					default = None;
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				      }
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				  ];
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			      };
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			    SigAssign {
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				lhs = "q";
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				rhs = Var "shft";
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				cond = None;
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			      }
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			  ];
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		      }];
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    configuration = None;
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  }
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