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lustrec / src / tools / importer / vhdl_deriving_yojson.ml @ 55963629

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let base_types = ["integer"; "character"; "bit"; "real"; "natural"; "positive"; "std_logic"; "std_logic_vector" ]
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type vhdl_type_t =
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  | Base of string
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  | Range of string option * int * int
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  | Bit_vector of int * int
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  | Array of int * int * vhdl_type_t
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  | Enumerated of string list
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[@@deriving yojson {strict = false}];;
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(************************************************************************************)		   
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(*                     Constants                                                    *)
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(************************************************************************************)		   
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(* Std_logic values :
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    'U': uninitialized. This signal hasn't been set yet.
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    'X': unknown. Impossible to determine this value/result.
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    '0': logic 0
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    '1': logic 1
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    'Z': High Impedance
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    'W': Weak signal, can't tell if it should be 0 or 1.
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    'L': Weak signal that should probably go to 0
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    'H': Weak signal that should probably go to 1
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    '-': Don't care. *)			       
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let std_logic_cst = ["U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ]
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(* TODO: do we need more constructors ? *)
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type cst_val_t = CstInt of int | CstStdLogic of string
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[@@deriving yojson {strict = false}];;
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(* TODO ? Shall we merge definition / declaration  *)
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type vhdl_definition_t =
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  | Type of {name : string ; definition: vhdl_type_t} [@name "Type"]
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  | Subtype of {name : string ; definition: vhdl_type_t} [@name "Subtype"]
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[@@deriving yojson {strict = false}];;
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type vhdl_declaration_t =
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  | VarDecl of { name : string; typ : vhdl_type_t; init_val : cst_val_t option } [@name "VarDecl"]
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  | CstDecl of { name : string; typ : vhdl_type_t; init_val : cst_val_t  } [@name "CstDecl"]
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  | SigDecl of { name : string; typ : vhdl_type_t; init_val : cst_val_t option } [@name "SigDecl"]
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[@@deriving yojson {strict = false}];;
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(************************************************************************************)		   
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(*            Attributes for types, arrays, signals and strings                     *)
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(************************************************************************************)		   
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type 'basetype vhdl_type_attributes_t =
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  | TAttNoArg of { id: string }
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  | TAttIntArg of { id: string; arg: int }
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  | TAttValArg of { id: string; arg: 'basetype }
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  | TAttStringArg of { id: string; arg: string }
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[@@deriving yojson {strict = false}];;
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let typ_att_noarg = ["base"; "left"; "right"; "high"; "low"]
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let typ_att_intarg = ["pos"; "val"; "succ"; "pred"; "leftof"; "rightof"]
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let typ_att_valarg = ["image"]
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let typ_att_stringarg = ["value"]
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type vhdl_array_attributes_t = AAttInt of { id: string; arg: int; } | AAttAscending
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[@@deriving yojson {strict = false}];;
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let array_att_intarg = ["left"; "right"; "high"; "low"; "range"; "reverse_range"; "length"]  
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type vhdl_signal_attributes_t = SigAtt of string
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[@@deriving yojson {strict = false}];;
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type vhdl_string_attributes_t = StringAtt of string
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[@@deriving yojson {strict = false}];;
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(************************************************************************************)		   
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(*                        Expressions  / Statements                                 *)
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(************************************************************************************)		   
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(* TODO: call to functions? procedures? *)  
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type vhdl_expr_t =
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  | Var of string (* a signal or a variable *)
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  | Op of { id: string; args: vhdl_expr_t list } 
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[@@deriving yojson {strict = false}];;
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let arith_funs = ["+";"-";"*";"/";"mod"; "rem";"abs";"**"]
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let bool_funs  = ["and"; "or"; "nand"; "nor"; "xor"; "not"]
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let rel_funs   = ["<";">";"<=";">=";"/=";"="]
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type vhdl_sequential_stmt_t = 
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  | VarAssign of { lhs: string; rhs: vhdl_expr_t }
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(*  | Case of { guard: vhdl_expr_t; branches: { case: }
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	    | Case of { guard: vhdl_expr_t; branches 
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 *)
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[@@deriving yojson {strict = false}];;
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type signal_condition_t =
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  {                            
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    expr: vhdl_expr_t;              (* when expression *)
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    else_case: vhdl_expr_t option;  (* optional else case expression. 
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                                             If None, could be a latch  *)
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  }
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[@@deriving yojson {strict = false}];;
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type signal_selection_t =
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  {
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    sel_lhs: string [@default ""];
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    expr : vhdl_expr_t;
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    when_sel: vhdl_expr_t option;
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  }
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[@@deriving yojson {strict = false}];;
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type conditional_signal_t =
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  {
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      lhs: string [@default ""];        (* assigned signal *)
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      rhs: vhdl_expr_t;                   (* expression *)
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      cond: signal_condition_t option     (* conditional signal statement *)
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  }
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[@@deriving yojson {strict = false}];;
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type process_t =
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  { 
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    id: string option [@default None];
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    active_sigs: string list [@default []];
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    body: vhdl_sequential_stmt_t list [@default []]
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  }
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[@@deriving yojson {strict = false}];;
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type selected_signal_t = 
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  { 
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    sel: vhdl_expr_t;  
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    branches: signal_selection_t list [@default []];
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  }
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[@@deriving yojson {strict = false}];;
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type vhdl_concurrent_stmt_t =
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  | SigAssign of conditional_signal_t 
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  | Process of process_t 
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  | SelectedSig of selected_signal_t
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[@@deriving yojson {strict = false}];;
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  (*
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type vhdl_statement_t =
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  (* | DeclarationStmt of declaration_stmt_t *)
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  | ConcurrentStmt of vhdl_concurrent_stmt_t
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  | SequentialStmt of vhdl_sequential_stmt_t
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   *)
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(************************************************************************************)		   
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(*                     Entities                                                     *)
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(************************************************************************************)		   
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(* TODO? Seems to appear optionally in entities *)
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type vhdl_generic_t = unit
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[@@deriving yojson {strict = false}];;
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type vhdl_port_kind_t = 
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    InPort     [@name "in"]
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  | OutPort    [@name "out"]
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  | InoutPort  [@name "inout"]
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  | BufferPort [@name "buffer"]
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[@@deriving yojson];;
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type vhdl_port_t =
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  {
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    names: string list [@default []];
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    kind: vhdl_port_kind_t;
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    typ : string;
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(*    typ: vhdl_type_t; *)
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  }
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[@@deriving yojson {strict = false}];;
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type vhdl_entity_t =
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  {
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    name: string [@default ""];
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    generics: vhdl_generic_t list option [@key "GENERIC_CLAUSE"] [@default Some []];
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    ports: vhdl_port_t list [@key "PORT_CLAUSE"] [@default []];
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  }
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[@@deriving yojson {strict = false}];;
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(************************************************************************************)		   
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(*                    Packages / Library loading                                    *)
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(************************************************************************************)		   
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(* Optional. Describes shared definitions *)
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type vhdl_package_t =
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  {
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    name: string [@default ""];
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    shared_defs: vhdl_definition_t list [@default []];
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  }
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[@@deriving yojson {strict = false}];;
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type vhdl_load_t = 
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    Library of string list [@name "LIBRARY_CLAUSE"] [@default ""]
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  | Use of string list [@name "USE_CLAUSE"] [@default []]
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[@@deriving yojson];;
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(************************************************************************************)		   
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(*                        Architecture / VHDL Design                                *)
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(************************************************************************************)		   
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type vhdl_architecture_t =
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  {
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    name: string [@default ""];
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    entity: string [@default ""];
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 (*   declarations: vhdl_declaration_t list option [@key "ARCHITECTURE_DECLARATIVE_PART"] [@default Some []];
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    body: vhdl_concurrent_stmt_t list option [@key "ARCHITECTURE_STATEMENT_PART"] [@default Some []]; *)
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  }
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[@@deriving yojson {strict = false}];;
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(* TODO. Configuration is optional *)
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type vhdl_configuration_t = unit
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[@@deriving yojson {strict = false}];;
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type vhdl_design_t =
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  {
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    packages: vhdl_package_t list [@key "PACKAGE_DECLARATION"] [@default []];
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    libraries: vhdl_load_t list option [@key "CONTEXT_CLAUSE"] [@default Some []];
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    entities: vhdl_entity_t list [@key "ENTITY_DECLARATION"] [@default []];
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    architectures: vhdl_architecture_t list [@key "ARCHITECTURE_BODY"] [@default []];
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    configuration: vhdl_configuration_t option [@key "CONFIGURATION_DECLARATION"] [@default Some ()];
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  }
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[@@deriving yojson {strict = false}];;
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type vhdl_design_file_t =
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  {
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    design_unit: vhdl_design_t list [@key "DESIGN_UNIT"] [@default []];
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  }
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[@@deriving yojson {strict = false}];;
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type vhdl_file_t = 
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  {
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    design_file: vhdl_design_file_t [@key "DESIGN_FILE"];
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  }
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[@@deriving yojson];;