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Revision 3d099916 src/backends/VHDL/vhdl_ast.ml

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src/backends/VHDL/vhdl_ast.ml
146 146
type vhdl_subprogram_spec_t =
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  {
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    name: string [@default ""];
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    subprogram_type: string [@default ""];
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    typeMark: vhdl_name_t [@default NoName];
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    parameters: vhdl_parameter_t list [@default []];
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    isPure: bool [@default false];
......
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      ports: vhdl_port_t list [@default []];
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    } [@name "COMPONENT_DECLARATION"]
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  | Subprogram of {
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      name: string [@default ""]; 
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      kind: string [@default ""]; 
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      spec: vhdl_subprogram_spec_t option [@default None]; 
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      spec: vhdl_subprogram_spec_t; 
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      decl_part: vhdl_declaration_t list [@default []]; 
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      stmts: vhdl_sequential_stmt_t list [@default []]
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    } [@name "SUBPROGRAM_BODY"]

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