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Revision 27332198 src/backends/VHDL/vhdl_ast.ml

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src/backends/VHDL/vhdl_ast.ml
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    delay: vhdl_expr_t option;
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_component_instantiation_t =
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  {
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    name: vhdl_name_t;
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    inst_unit: vhdl_name_t;
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    generic_map: vhdl_assoc_element_t option [@default None];
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    port_map: vhdl_assoc_element_t option [@default None];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type vhdl_concurrent_stmt_t =
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  | SigAssign of vhdl_conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
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  | Process of vhdl_process_t [@name "PROCESS_STATEMENT"]
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  | SelectedSig of vhdl_selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
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  | ComponentInst of vhdl_component_instantiation_t [@name "COMPONENT_INSTANTIATION_STATEMENT"]
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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  (*
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type vhdl_statement_t =

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