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Revision 00970bbf src/backends/VHDL/vhdl_ast.ml

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src/backends/VHDL/vhdl_ast.ml
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  | NoName
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and vhdl_assoc_element_t =
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  {
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    formal_name: vhdl_name_t option [@default Some NoName];
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    formal_arg: vhdl_name_t option [@default Some NoName];
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    actual_name: vhdl_name_t option [@default Some NoName];
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    actual_designator: vhdl_name_t option [@default Some NoName];
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    actual_expr: vhdl_expr_t option [@default Some IsNull];
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    formal_name: vhdl_name_t option [@default None];
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    formal_arg: vhdl_name_t option [@default None];
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    actual_name: vhdl_name_t option [@default None];
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    actual_designator: vhdl_name_t option [@default None];
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    actual_expr: vhdl_expr_t option [@default None];
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  }
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and vhdl_element_assoc_t =
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  {
......
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    names: vhdl_name_t list;
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    mode: string list [@default []];
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    typ: vhdl_subtype_indication_t;
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    init_val: vhdl_cst_val_t option [@default Some (CstInt (0))];
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    init_val: vhdl_cst_val_t option [@default None];
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  }
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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......
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  | VarDecl of {
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : vhdl_cst_val_t option [@default Some (CstInt (0))] 
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      init_val : vhdl_cst_val_t option [@default None] 
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    } [@name "VARIABLE_DECLARATION"]
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  | CstDecl of { 
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      names : vhdl_name_t list; 
......
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  | SigDecl of { 
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : vhdl_cst_val_t option [@default Some (CstInt (0))] 
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      init_val : vhdl_cst_val_t option [@default None] 
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    } [@name "SIGNAL_DECLARATION"]
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  | Subprogram of {
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      name: vhdl_name_t [@default NoName]; 

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