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Revision fae1790f

Added by Arnaud Dieumegard over 5 years ago

Added support for Process statements, signal assignment, If, Exit and Null sequential statements

View differences:

src/tools/importer/vhdl_deriving_yojson.ml
78 78 
(************************************************************************************)
79 79 
(*                        Expressions  / Statements                                 *)
80 80 
(************************************************************************************)
81 
type suffix_selection_t = Idx of int | Range of int * int
82 
[@@deriving yojson {strict = false}];;
81 83 

  		




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(* TODO: call to functions? procedures? *)  


  		




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type vhdl_expr_t =


  		




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  | Var of string (* a signal or a variable *)


  		




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  | Op of { id: string; args: vhdl_expr_t list } 


  		




  
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  | Op of { id: string; args: vhdl_expr_t list } [@name "Expression"]


  		




  
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  | IsNull


  		




  
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  | Time of { value: int; phy_unit: string }


  		




  
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  | Sig of { name: string; att: vhdl_signal_attributes_t option }


  		




  
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  | SuffixMod of { expr : vhdl_expr_t; selection : suffix_selection_t }


  		




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[@@deriving yojson {strict = false}];;


  		




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let arith_funs = ["+";"-";"*";"/";"mod"; "rem";"abs";"**"]


  		




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let bool_funs  = ["and"; "or"; "nand"; "nor"; "xor"; "not"]


  		




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let rel_funs   = ["<";">";"<=";">=";"/=";"="]


  		




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type vhdl_sequential_stmt_t = 


  		




  
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type vhdl_if_case_t = 


  		




  
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  {


  		




  
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    if_cond: vhdl_expr_t;


  		




  
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    if_block: vhdl_sequential_stmt_t list;


  		




  
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  }	   


  		




  
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and vhdl_sequential_stmt_t = 


  		




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  | VarAssign of { lhs: string; rhs: vhdl_expr_t }


  		




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(*  | Case of { guard: vhdl_expr_t; branches: { case: }


  		




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	    | Case of { guard: vhdl_expr_t; branches 


  		




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 *)


  		




  
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  | SigSeqAssign of { label: string option; lhs: string; rhs: vhdl_expr_t list} [@name "SIGNAL_ASSIGNMENT_STATEMENT"]


  		




  
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  | If of { label: string option [@default Some ""]; if_cases: vhdl_if_case_t list;


  		




  
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    default: (vhdl_sequential_stmt_t list) option; } [@name "IF_STATEMENT"]


  		




  
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  | Case of { guard: vhdl_expr_t; branches: vhdl_case_item_t list }


  		




  
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  | Exit of { label: string option [@default Some ""]; loop_label: string option [@default Some ""]; condition: vhdl_expr_t option [@default Some IsNull]} [@name "EXIT_STATEMENT"]


  		




  
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  | Null of { label: string option [@default Some ""]} [@name "NULL_STATEMENT"]


  		




  
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and vhdl_case_item_t = 


  		




  
  112
  
    
  {


  		




  
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    when_cond: vhdl_expr_t;


  		




  
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    when_stmt: vhdl_sequential_stmt_t;


  		




  
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  }


  		




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[@@deriving yojson {strict = false}];;


  		




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type signal_condition_t =


  		




  ......




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type conditional_signal_t =


  		




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  {


  		




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      lhs: string [@default ""];        (* assigned signal *)


  		




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      rhs: vhdl_expr_t;                   (* expression *)


  		




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      cond: signal_condition_t option     (* conditional signal statement *)


  		




  
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    lhs: string [@default ""];        (* assigned signal = target*)


  		




  
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    rhs: vhdl_expr_t;                   (* expression *)


  		




  
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    cond: signal_condition_t option;     (* conditional signal statement = waveform*)


  		




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  }


  		




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[@@deriving yojson {strict = false}];;


  		




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type process_t =


  		




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  { 


  		




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    id: string option [@default None];


  		




  
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    declarations: vhdl_declaration_t list option [@key "PROCESS_DECLARATIVE_PART"] [@default Some []];


  		




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    active_sigs: string list [@default []];


  		




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    body: vhdl_sequential_stmt_t list [@default []]


  		




  
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    body: vhdl_sequential_stmt_t list [@key "PROCESS_STATEMENT_PART"] [@default []]


  		




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  }


  		




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[@@deriving yojson {strict = false}];;


  		




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  ......




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[@@deriving yojson {strict = false}];;


  		




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type vhdl_concurrent_stmt_t =


  		




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  | SigAssign of conditional_signal_t 


  		




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  | Process of process_t 


  		




  
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  | SigAssign of conditional_signal_t [@key "SIGNAL_ASSIGNMENT"]


  		




  
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  | Process of process_t [@key "PROCESS_STATEMENT"]


  		




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  | SelectedSig of selected_signal_t


  		




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[@@deriving yojson {strict = false}];;


  		




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  (*


  		












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