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Revision e15a8d65

Added by Arnaud Dieumegard over 4 years ago

Added open in vhdl ast

View differences:

src/backends/VHDL/vhdl_ast.ml
85 85 
  | Slice of { id: vhdl_name_t; range: vhdl_discrete_range_t } [@name "SLICE_NAME"]
86 86 
  | Attribute of { id: vhdl_name_t; designator: vhdl_name_t; expr: vhdl_expr_t [@default IsNull]} [@name "ATTRIBUTE_NAME"]
87 87 
  | Function of { id: vhdl_name_t; assoc_list: vhdl_assoc_element_t list } [@name "FUNCTION_CALL"]
88 
  | Open [@name "OPEN"]
88 89 
  | NoName
89 90 
and vhdl_assoc_element_t =
90 91 
  {
src/tools/importer/mini_vhdl_check.ml
3 3 
open Vhdl_2_mini_vhdl_map
4 4 
open Mini_vhdl_utils
5 5 

  		




  6
  
  
    
(*


  		




  7
  
  
    
type db_tuple_t =


  		




  8
  
  
    
  {


  		




  9
  
  
    
    mutable entity: vhdl_entity_t;


  		




  10
  
  
    
    mutable architecture: vhdl_architecture_t;


  		




  11
  
  
    
    mutable architecture_signals: mini_vhdl_declaration_t list;


  		




  12
  
  
    
    mutable architecture_ports: vhdl_port_t list;


  		




  13
  
  
    
    mutable architecture_generics: vhdl_port_t list;


  		




  14
  
  
    
    mutable assigned_signals_names: vhdl_name_t list;


  		




  15
  
  
    
    mutable contexts: vhdl_load_t list;


  		




  16
  
  
    
  }


  		




  17
  
  
    
*)


  		




  18
  
  
    

  		




  19
  6
  
    
type level = INFO | WARNING | ERROR


  		




  20
  7
  
    

  		




  21
  8
  
    
let print ?(level = INFO) ?(code = "") s =


  		




  ......




  35
  22
  
    
 *)


  		




  36
  23
  
    
let display_struct_content : (vhdl_name_t -> string) -> db_tuple_t -> unit =


  		




  37
  24
  
    
  fun to_string_name ->


  		




  38
  
  
    
    fun {entity; architecture; architecture_signals; architecture_ports; architecture_generics; assigned_signals_names; contexts} ->


  		




  
  25
  
    
    fun {entity; architecture; architecture_signals; architecture_ports; architecture_generics; assigned_signals_names; memories; contexts} ->


  		




  39
  26
  
    
      let arch_name = to_string_name architecture.name in


  		




  40
  27
  
    
      let ent_name = to_string_name entity.name in


  		




  41
  28
  
    
      let sigs_names = List.flatten (List.map mini_vhdl_declaration_t_names architecture_signals) in


  		




  ......




  49
  36
  
    
      print (filter_display "  InOut ports" inout_ports_names to_string_name);


  		




  50
  37
  
    
      print (filter_display "  Out ports" out_ports_names to_string_name);


  		




  51
  38
  
    
      print (filter_display "  Generics" generics_names to_string_name);


  		




  52
  
  
    
      print (filter_display "  Assigned names" (List.sort_uniq compare assigned_signals_names) to_string_name)


  		




  
  39
  
    
      print (filter_display "  Assigned names" (List.sort_uniq compare assigned_signals_names) to_string_name);


  		




  
  40
  
    
      print (filter_display "  Memories" (List.sort_uniq compare memories) to_string_name)


  		




  53
  41
  
    

  		




  54
  42
  
    
(**


  		




  55
  43
  
    
 * Checks


  		




  ......




  72
  60
  
    
        let sigs_names = List.flatten (List.map mini_vhdl_declaration_t_names architecture_signals) in


  		




  73
  61
  
    
        let declared_signals = inout_ports_names@sigs_names@out_ports_names in


  		




  74
  62
  
    
        let uniq_assigned_signals = List.sort_uniq compare assigned_signals_names in


  		




  75
  
  
    
        let missing = diff declared_signals uniq_assigned_signals to_string_name in


  		




  
  63
  
    
        let missing = diff declared_signals uniq_assigned_signals in


  		




  76
  64
  
    
        if List.length missing > 0


  		




  77
  65
  
    
          then print ~level:level ~code:code (Printf.sprintf " Missing assignment of %s" (filter_display "signal" missing to_string_name))


  		




  78
  66
  
    
          else ()


  		












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