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Revision dea84f9e

Added by Pierre-Loïc Garoche about 5 years ago

Working example!

View differences:

src/backends/VHDL/vhdl_test.ml
33 33 
				id = None;
34 34 
				active_sigs = ["clk"; "rst"];
35 35 
				body = [
36
36 
				    If {
37 
					if_cases = [
38 
					  {
39 
					    if_cond = Sig{ name = "rst"; att = None };
40 
					    if_block = [
41 
						SigSeqAssign { lhs = "req"; rhs = Cst (CstBV("x", "00"))};
42 
						SigSeqAssign { lhs = "shft"; rhs = Cst (CstBV("x", "00"))};
43 
					      ];
44 
					  };
45 
					  {
46 
					    if_cond = Op {id = "and"; args = [Sig{ name = "clk"; att = None };
47 
									      Sig{ name = "clk"; att = Some (SigAtt "event") }]};
48 
					    if_block = [
49 
						SigSeqAssign { lhs = "req"; rhs = Op { id = "&"; args = [
50 
											   Sig{ name = "s0"; att = None };
51 
											   Sig{ name = "s1"; att = None }
52 
											 ]
53 
										     }
54 
							     };
55 
						Case {
56 
						    guard = Sig{ name = "sel"; att = None };
57 
						    branches = [
58 
							{
59 
							  when_cond = Cst (CstBV("b", "00"));
60 
							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d0"; att = None }};
61 
							};
62 
							{
63 
							  when_cond = Cst (CstBV("b", "10"));
64 
							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d1"; att = None }};
65 
							};
66 
							{
67 
							  when_cond = Cst (CstBV("b", "01"));
68 
							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d2"; att = None }};
69 
							};
70 
							{
71 
							  when_cond = Cst (CstBV("b", "11"));
72 
							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d3"; att = None }};
73 
							};
74 

  		




  
  75
  
    
						      ]


  		




  
  76
  
    

  		




  
  77
  
    
						  };


  		




  
  78
  
    
						If {


  		




  
  79
  
    
						    if_cases = [


  		




  
  80
  
    
						      {


  		




  
  81
  
    
							if_cond = Sig{ name = "s_1"; att = None };


  		




  
  82
  
    
							if_block = [


  		




  
  83
  
    
							    SigSeqAssign {


  		




  
  84
  
    
								lhs = "shft";


  		




  
  85
  
    
								rhs = Op { id = "&";


  		




  
  86
  
    
									   args = [


  		




  
  87
  
    
									       SuffixMod {


  		




  
  88
  
    
										   expr = Sig{ name = "shft"; att = None };


  		




  
  89
  
    
										   selection = Range (6,0);


  		




  
  90
  
    
										 };


  		




  
  91
  
    
									       SuffixMod {


  		




  
  92
  
    
										   expr = Sig{ name = "shft"; att = None };


  		




  
  93
  
    
										   selection = Idx 7;


  		




  
  94
  
    
										 }


  		




  
  95
  
    
									     ]


  		




  
  96
  
    
									 }


  		




  
  97
  
    
							      };


  		




  
  98
  
    
							  ];


  		




  
  99
  
    
						      };


  		




  
  100
  
    
						    ];


  		




  
  101
  
    
						    default = Some [


  		




  
  102
  
    
								  SigSeqAssign { lhs = "shft"; rhs = Var "reg"};


  		




  
  103
  
    
								]


  		




  
  104
  
    
						  };


  		




  
  105
  
    
					      ];


  		




  
  106
  
    
					  };


  		




  
  107
  
    
					  


  		




  
  108
  
    
					];


  		




  
  109
  
    
					default = None;


  		




  
  110
  
    
				      }


  		




  37
  111
  
    
				  ];


  		




  38
  112
  
    
			      };


  		




  39
  113
  
    
			    SigAssign {


  		












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