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let base_types =
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  [
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    "integer";
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    "character";
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    "bit";
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    "real";
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    "natural";
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    "positive";
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    "std_logic";
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    "std_logic_vector";
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  ]
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type vhdl_type_t =
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  | Base of string
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  | Range of string option * int * int [@name "RANGE_WITH_DIRECTION"]
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  | Bit_vector of int * int
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  | Array of int * int * vhdl_type_t
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  | Enumerated of string list
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  | Void
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[@@deriving yojson]
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(************************************************************************************)
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(* Constants *)
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(************************************************************************************)
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(* Std_logic values : 'U': uninitialized. This signal hasn't been set yet. 'X':
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   unknown. Impossible to determine this value/result. '0': logic 0 '1': logic 1
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   'Z': High Impedance 'W': Weak signal, can't tell if it should be 0 or 1. 'L':
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   Weak signal that should probably go to 0 'H': Weak signal that should
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   probably go to 1 '-': Don't care. *)
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let std_logic_cst = [ "U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ]
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let literal_base = [ "B"; "O"; "X"; "UB"; "UO"; "UX"; "SB"; "SO"; "SX"; "D" ]
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(* Prefix of CstLiteral *)
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(* TODO: do we need more constructors ? *)
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type cst_val_t =
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  | CstInt of int
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  | CstStdLogic of string
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  | CstLiteral of string [@name "CST_LITERAL"]
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[@@deriving yojson { strict = false }]
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type vhdl_subtype_indication_t = {
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  name : string;
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  definition : vhdl_type_t option; [@default Some Void]
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}
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[@@deriving yojson { strict = false }]
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(* TODO ? Shall we merge definition / declaration *)
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type vhdl_definition_t =
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  | Type of { name : string; definition : vhdl_type_t }
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      [@name "TYPE_DECLARATION"]
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  | Subtype of { name : string; typ : vhdl_subtype_indication_t }
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      [@name "SUBTYPE_DECLARATION"]
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[@@deriving yojson { strict = false }]
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type vhdl_declaration_t =
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  | VarDecl of {
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      names : string list;
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      typ : vhdl_subtype_indication_t;
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      init_val : cst_val_t option; [@default Some (CstInt 0)]
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    } [@name "VARIABLE_DECLARATION"]
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  | CstDecl of {
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      names : string list;
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      typ : vhdl_subtype_indication_t;
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      init_val : cst_val_t;
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    } [@name "CONSTANT_DECLARATION"]
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  | SigDecl of {
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      names : string list;
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      typ : vhdl_subtype_indication_t;
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      init_val : cst_val_t option; [@default Some (CstInt 0)]
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    } [@name "SIGNAL_DECLARATION"]
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[@@deriving yojson { strict = false }]
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(************************************************************************************)
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(* Attributes for types, arrays, signals and strings *)
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(************************************************************************************)
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type 'basetype vhdl_type_attributes_t =
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  | TAttNoArg of { id : string }
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  | TAttIntArg of { id : string; arg : int }
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  | TAttValArg of { id : string; arg : 'basetype }
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  | TAttStringArg of { id : string; arg : string }
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[@@deriving yojson { strict = false }]
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let typ_att_noarg = [ "base"; "left"; "right"; "high"; "low" ]
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let typ_att_intarg = [ "pos"; "val"; "succ"; "pred"; "leftof"; "rightof" ]
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let typ_att_valarg = [ "image" ]
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let typ_att_stringarg = [ "value" ]
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type vhdl_array_attributes_t =
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  | AAttInt of { id : string; arg : int }
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  | AAttAscending
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[@@deriving yojson { strict = false }]
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let array_att_intarg =
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  [ "left"; "right"; "high"; "low"; "range"; "reverse_range"; "length" ]
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type vhdl_signal_attributes_t = SigAtt of string
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[@@deriving yojson { strict = false }]
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type vhdl_string_attributes_t = StringAtt of string
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[@@deriving yojson { strict = false }]
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(************************************************************************************)
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(* Expressions / Statements *)
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(************************************************************************************)
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type suffix_selection_t = Idx of int | Range of int * int
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[@@deriving yojson { strict = false }]
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type vhdl_expr_t =
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  | Call of vhdl_name_t [@name "CALL"]
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  | Cst of cst_val_t [@name "CONSTANT_VALUE"]
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  | Op of { id : string; [@default ""] args : vhdl_expr_t list [@default []] }
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      [@name "EXPRESSION"]
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  | IsNull [@name "IsNull"]
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  | Time of { value : int; phy_unit : string [@default ""] }
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  | Sig of { name : string; att : vhdl_signal_attributes_t option }
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  | SuffixMod of { expr : vhdl_expr_t; selection : suffix_selection_t }
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[@@deriving yojson { strict = false }]
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and vhdl_name_t =
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  | Simple of string [@name "SIMPLE_NAME"]
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  | Selected of vhdl_name_t list [@name "SELECTED_NAME"]
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  | Index of { id : vhdl_name_t; exprs : vhdl_expr_t list }
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      [@name "INDEXED_NAME"]
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  | Slice of { id : vhdl_name_t; range : vhdl_type_t } [@name "SLICE_NAME"]
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  | Attribute of {
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      id : vhdl_name_t;
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      designator : vhdl_name_t;
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      expr : vhdl_expr_t; [@default IsNull]
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    } [@name "ATTRIBUTE_NAME"]
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  | Function of { id : vhdl_name_t; assoc_list : vhdl_assoc_element_t list }
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      [@name "FUNCTION_CALL"]
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  | NoName
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[@@deriving yojson { strict = false }]
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and vhdl_assoc_element_t = {
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  formal_name : vhdl_name_t option; [@default Some NoName]
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  formal_arg : vhdl_name_t option; [@default Some NoName]
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  actual_name : vhdl_name_t option; [@default Some NoName]
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  actual_designator : vhdl_name_t option; [@default Some NoName]
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  actual_expr : vhdl_expr_t option; [@default Some IsNull]
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}
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[@@deriving yojson { strict = false }]
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let arith_funs = [ "+"; "-"; "*"; "/"; "mod"; "rem"; "abs"; "**"; "&" ]
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let bool_funs = [ "and"; "or"; "nand"; "nor"; "xor"; "not" ]
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let rel_funs =
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  [
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    "<"; ">"; "<="; ">="; "/="; "="; "?="; "?/="; "?<"; "?<="; "?>"; "?>="; "??";
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  ]
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let shift_funs = [ "sll"; "srl"; "sla"; "sra"; "rol"; "ror" ]
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type vhdl_sequential_stmt_t =
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  | VarAssign of { lhs : vhdl_name_t; rhs : vhdl_expr_t }
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  | SigSeqAssign of {
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      label : string; [@default ""]
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      lhs : vhdl_name_t;
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      rhs : vhdl_expr_t list;
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    } [@name "SIGNAL_ASSIGNMENT_STATEMENT"]
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  | If of {
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      label : string; [@default ""]
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      if_cases : vhdl_if_case_t list;
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      default : vhdl_sequential_stmt_t list; [@default []]
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    } [@name "IF_STATEMENT"]
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  | Case of { guard : vhdl_expr_t; branches : vhdl_case_item_t list }
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      [@name "CASE_STATEMENT_TREE"]
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  | Exit of {
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      label : string; [@default ""]
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      loop_label : string option; [@default Some ""]
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      condition : vhdl_expr_t option; [@default Some IsNull]
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    } [@name "EXIT_STATEMENT"]
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  | Assert of {
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      label : string; [@default ""]
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      cond : vhdl_expr_t;
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      report : vhdl_expr_t; [@default IsNull]
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      severity : vhdl_expr_t; [@default IsNull]
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    } [@name "ASSERTION_STATEMENT"]
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  | Wait [@name "WAIT_STATEMENT"]
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  | Null of { label : string [@default ""] } [@name "NULL_STATEMENT"]
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and vhdl_if_case_t = {
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  if_cond : vhdl_expr_t;
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  if_block : vhdl_sequential_stmt_t list;
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}
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and vhdl_case_item_t = {
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  when_cond : vhdl_expr_t list;
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  when_stmt : vhdl_sequential_stmt_t list;
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}
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[@@deriving yojson { strict = false }]
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type signal_condition_t = {
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  expr : vhdl_expr_t list;
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  (* when expression *)
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  cond : vhdl_expr_t; [@default IsNull]
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      (* optional else case expression. If None, could be a latch *)
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}
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[@@deriving yojson { strict = false }]
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type signal_selection_t = {
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  expr : vhdl_expr_t;
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  when_sel : vhdl_expr_t list; [@default []]
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}
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[@@deriving yojson { strict = false }]
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type conditional_signal_t = {
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  postponed : bool; [@default false]
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  label : string option; [@default Some ""]
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  lhs : vhdl_name_t;
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  (* assigned signal = target*)
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  rhs : signal_condition_t list;
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  (* expression *)
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  cond : vhdl_expr_t; [@default IsNull]
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  delay : vhdl_expr_t; [@default IsNull]
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}
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[@@deriving yojson { strict = false }]
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type process_t = {
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  id : string option; [@default Some ""]
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  declarations : vhdl_declaration_t list option;
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      [@key "PROCESS_DECLARATIVE_PART"] [@default Some []]
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  active_sigs : vhdl_name_t list; [@default []]
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  body : vhdl_sequential_stmt_t list;
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      [@key "PROCESS_STATEMENT_PART"] [@default []]
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}
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[@@deriving yojson { strict = false }]
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type selected_signal_t = {
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  postponed : bool; [@default false]
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  label : string option; [@default Some ""]
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  lhs : vhdl_name_t;
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  (* assigned signal = target *)
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  sel : vhdl_expr_t;
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  branches : signal_selection_t list; [@default []]
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  delay : vhdl_expr_t option;
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}
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[@@deriving yojson { strict = false }]
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type vhdl_concurrent_stmt_t =
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  | SigAssign of conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
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  | Process of process_t [@name "PROCESS_STATEMENT"]
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  | SelectedSig of selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
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[@@deriving yojson { strict = false }]
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(* type vhdl_statement_t =
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   (* | DeclarationStmt of declaration_stmt_t *) | ConcurrentStmt of
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   vhdl_concurrent_stmt_t | SequentialStmt of vhdl_sequential_stmt_t *)
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(************************************************************************************)
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(* Entities *)
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(************************************************************************************)
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(* TODO? Seems to appear optionally in entities *)
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type vhdl_generic_t = unit [@@deriving yojson { strict = false }]
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type vhdl_port_kind_t =
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  | InPort [@name "in"]
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  | OutPort [@name "out"]
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  | InoutPort [@name "inout"]
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  | BufferPort [@name "buffer"]
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[@@deriving yojson]
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type vhdl_port_t = {
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  names : string list; [@default []]
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  kind : vhdl_port_kind_t;
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  typ : string; (* typ: vhdl_type_t; *)
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}
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[@@deriving yojson { strict = false }]
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type vhdl_entity_t = {
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  name : string; [@default ""]
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  generics : vhdl_generic_t list option;
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      [@key "GENERIC_CLAUSE"] [@default Some []]
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  ports : vhdl_port_t list; [@key "PORT_CLAUSE"] [@default []]
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}
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[@@deriving yojson { strict = false }]
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(************************************************************************************)
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(* Packages / Library loading *)
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(************************************************************************************)
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(* Optional. Describes shared definitions *)
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type vhdl_package_t = {
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  name : string; [@default ""]
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  shared_defs : vhdl_definition_t list; [@default []]
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}
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[@@deriving yojson { strict = false }]
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type vhdl_load_t =
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  | Library of string list [@name "LIBRARY_CLAUSE"] [@default ""]
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  | Use of string list [@name "USE_CLAUSE"] [@default []]
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[@@deriving yojson]
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(************************************************************************************)
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(* Architecture / VHDL Design *)
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(************************************************************************************)
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type vhdl_architecture_t = {
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  name : string; [@default ""]
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  entity : string; [@default ""]
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  declarations : vhdl_declaration_t list option;
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      [@key "ARCHITECTURE_DECLARATIVE_PART"] [@default Some []]
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  body : vhdl_concurrent_stmt_t list option;
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      [@key "ARCHITECTURE_STATEMENT_PART"] [@default Some []]
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}
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[@@deriving yojson { strict = false }]
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(* TODO. Configuration is optional *)
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type vhdl_configuration_t = unit [@@deriving yojson { strict = false }]
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type vhdl_design_t = {
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  packages : vhdl_package_t list; [@key "PACKAGE_DECLARATION"] [@default []]
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  libraries : vhdl_load_t list option;
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      [@key "CONTEXT_CLAUSE"] [@default Some []]
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  entities : vhdl_entity_t list; [@key "ENTITY_DECLARATION"] [@default []]
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  architectures : vhdl_architecture_t list;
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      [@key "ARCHITECTURE_BODY"] [@default []]
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  configuration : vhdl_configuration_t option;
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      [@key "CONFIGURATION_DECLARATION"] [@default Some ()]
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}
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[@@deriving yojson { strict = false }]
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type vhdl_design_file_t = {
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  design_unit : vhdl_design_t list; [@key "DESIGN_UNIT"] [@default []]
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}
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[@@deriving yojson { strict = false }]
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type vhdl_file_t = { design_file : vhdl_design_file_t [@key "DESIGN_FILE"] }
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[@@deriving yojson]
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