Project

General

Profile

Download (2.28 KB) Statistics
| Branch: | Tag: | Revision:
1
(* An application that loads json provided input and produces Lustre
2

    
3
   Usage: lustrei -vhdl myvhdl.json lustrei -scade myscademodel.json will
4
   produce a lustre file that can be compiled and analyzed
5

    
6
   VHDL is handled in a double way: as a backend and as an import language In a
7
   first step, lustrei -vhdl -print myvhdl.json shall print the VHDL model in
8
   stdout *)
9
(* open Vhdl_ast open Vhdl_test *)
10
open Yojson.Safe
11
open Vhdl_deriving_yojson
12
open Vhdl_json_lib
13

    
14
let () =
15
  (* (* Load model with Yojson *) let json = xx in
16

    
17
     (* Create VHDL values *) let vhdl : vhdl_design_t = xxxx json in
18

    
19
     (* Printing result *) Format.printf "Loaded VHDL:@.%a@." pp_vhdl_design
20
     vhdl *)
21
  let vhdl_json = from_file Sys.argv.(1) in
22
  Format.printf "Original file:\n%s\n\n" (pretty_to_string vhdl_json);
23

    
24
  (*let vhdl = design1 in Format.printf "Loaded VHDL:@.%a@." pp_vhdl_design
25
    vhdl;*)
26
  let vhdl1_json =
27
    vhdl_json |> prune_str "TOKEN" |> prune_str "IDENTIFIER"
28
    |> prune_str "SUBTYPE_INDICATION"
29
    |> prune_null_assoc
30
    |> to_list_content_str "DESIGN_UNIT"
31
    |> to_list_content_str "INTERFACE_VARIABLE_DECLARATION"
32
    |> flatten_ivd |> flatten_numeric_literal
33
    |> to_list_str "ENTITY_DECLARATION"
34
    |> to_list_str "ARCHITECTURE_BODY"
35
    |> to_list_str "PACKAGE_DECLARATION"
36
  in
37
  Format.printf "Preprocessed json:\n";
38
  Format.printf "%s\n\n" (pretty_to_string vhdl1_json);
39

    
40
  (* List.iter (Format.printf "%s\n") (print_depth vhdl1_json 7 ""); *)
41
  to_file (Sys.argv.(1) ^ ".out.json") vhdl1_json;
42

    
43
  (* let typ = {name = "type"; definition = (Some (Range (Some "toto", 7, 0)))}
44
     in Format.printf "\nModel to string\n%s\n\n" (pretty_to_string
45
     (vhdl_subtype_indication_t_to_yojson typ));
46

    
47
     let elem = "[\"SUBTYPE_DECLARATION\", {\"name\": \"byte\", \"typ\": {
48
     \"name\": \"bit_vector\", \"definition\": [ \"RANGE_WITH_DIRECTION\",
49
     \"downto\", 7, 0 ]}}]" in match vhdl_definition_t_of_yojson (from_string
50
     elem) with Ok x -> Format.printf "\nString to string\n%s\n\n"
51
     (pretty_to_string (vhdl_definition_t_to_yojson x)); | Error e ->
52
     Format.printf "Error: %s\n" e; *)
53
  match vhdl_file_t_of_yojson vhdl1_json with
54
  | Ok x ->
55
    Format.printf "Parsed VHDL: \n%s\n"
56
      (pretty_to_string (vhdl_file_t_to_yojson x))
57
  | Error e ->
58
    Format.printf "Error: %s\n" e
(1-1/3)