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open Vhdl_ast
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let design1 =
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  {
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    packages =
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      [
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        {
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          name = "typedef";
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          shared_defs =
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            [ Subtype { name = "byte"; definition = Bit_vector (7, 0) } ];
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        };
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      ];
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    libraries = [ Use [ "work"; "typedef"; "all" ] ];
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    entities =
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      [
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        {
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          name = "data_path";
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          generics = [];
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          ports =
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            [
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              { name = "clk"; kind = InPort; typ = Base "boolean" };
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              { name = "rst"; kind = InPort; typ = Base "boolean" };
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              { name = "s_1"; kind = InPort; typ = Base "boolean" };
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              { name = "s0"; kind = InPort; typ = Base "bit" };
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              { name = "s1"; kind = InPort; typ = Base "bit" };
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              { name = "d0"; kind = InPort; typ = Base "byte" };
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              { name = "d1"; kind = InPort; typ = Base "byte" };
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              { name = "d2"; kind = InPort; typ = Base "byte" };
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              { name = "d3"; kind = InPort; typ = Base "byte" };
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              { name = "q"; kind = OutPort; typ = Base "byte" };
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            ];
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        };
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      ];
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    architectures =
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      [
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        {
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          name = "behavior";
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          entity = "data_path";
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          declarations =
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            [
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              SigDecl { name = "reg"; typ = Base "byte"; init_val = None };
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              SigDecl { name = "shft"; typ = Base "byte"; init_val = None };
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              SigDecl { name = "sel"; typ = Bit_vector (1, 0); init_val = None };
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            ];
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          body =
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            [
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              Process
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                {
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                  id = None;
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                  active_sigs = [ "clk"; "rst" ];
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                  body =
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                    [
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                      If
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                        {
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                          if_cases =
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                            [
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                              {
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                                if_cond = Sig { name = "rst"; att = None };
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                                if_block =
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                                  [
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                                    SigSeqAssign
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                                      {
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                                        lhs = "req";
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                                        rhs = Cst (CstBV ("x", "00"));
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                                      };
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                                    SigSeqAssign
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                                      {
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                                        lhs = "shft";
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                                        rhs = Cst (CstBV ("x", "00"));
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                                      };
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                                  ];
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                              };
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                              {
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                                if_cond =
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                                  Op
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                                    {
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                                      id = "and";
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                                      args =
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                                        [
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                                          Sig { name = "clk"; att = None };
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                                          Sig
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                                            {
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                                              name = "clk";
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                                              att = Some (SigAtt "event");
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                                            };
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                                        ];
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                                    };
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                                if_block =
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                                  [
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                                    SigSeqAssign
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                                      {
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                                        lhs = "req";
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                                        rhs =
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                                          Op
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                                            {
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                                              id = "&";
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                                              args =
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                                                [
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                                                  Sig
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                                                    { name = "s0"; att = None };
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                                                  Sig
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                                                    { name = "s1"; att = None };
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                                                ];
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                                            };
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                                      };
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                                    Case
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                                      {
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                                        guard = Sig { name = "sel"; att = None };
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                                        branches =
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                                          [
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                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "00"));
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                                              when_stmt =
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                                                SigSeqAssign
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                                                  {
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                                                    lhs = "req";
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                                                    rhs =
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                                                      Sig
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                                                        {
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                                                          name = "d0";
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                                                          att = None;
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                                                        };
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                                                  };
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                                            };
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                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "10"));
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                                              when_stmt =
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                                                SigSeqAssign
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                                                  {
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                                                    lhs = "req";
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                                                    rhs =
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                                                      Sig
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                                                        {
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                                                          name = "d1";
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                                                          att = None;
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                                                        };
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                                                  };
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                                            };
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                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "01"));
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                                              when_stmt =
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                                                SigSeqAssign
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                                                  {
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                                                    lhs = "req";
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                                                    rhs =
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                                                      Sig
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                                                        {
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                                                          name = "d2";
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                                                          att = None;
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                                                        };
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                                                  };
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                                            };
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                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "11"));
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                                              when_stmt =
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                                                SigSeqAssign
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                                                  {
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                                                    lhs = "req";
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                                                    rhs =
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                                                      Sig
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                                                        {
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                                                          name = "d3";
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                                                          att = None;
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                                                        };
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                                                  };
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                                            };
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                                          ];
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                                      };
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                                    If
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                                      {
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                                        if_cases =
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                                          [
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                                            {
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                                              if_cond =
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                                                Sig { name = "s_1"; att = None };
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                                              if_block =
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                                                [
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                                                  SigSeqAssign
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                                                    {
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                                                      lhs = "shft";
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                                                      rhs =
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                                                        Op
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                                                          {
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                                                            id = "&";
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                                                            args =
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                                                              [
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                                                                SuffixMod
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                                                                  {
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                                                                    expr =
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                                                                      Sig
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                                                                        {
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                                                                          name =
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                                                                            "shft";
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                                                                          att =
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                                                                            None;
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                                                                        };
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                                                                    selection =
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                                                                      Range
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                                                                        (6, 0);
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                                                                  };
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                                                                SuffixMod
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                                                                  {
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                                                                    expr =
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                                                                      Sig
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                                                                        {
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                                                                          name =
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                                                                            "shft";
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                                                                          att =
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                                                                            None;
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                                                                        };
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                                                                    selection =
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                                                                      Idx 7;
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                                                                  };
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                                                              ];
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                                                          };
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                                                    };
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                                                ];
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                                            };
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                                          ];
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                                        default =
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                                          Some
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                                            [
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                                              SigSeqAssign
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                                                {
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                                                  lhs = "shft";
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                                                  rhs = Var "reg";
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                                                };
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                                            ];
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                                      };
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                                  ];
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                              };
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                            ];
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                          default = None;
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                        };
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                    ];
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                };
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              SigAssign { lhs = "q"; rhs = Var "shft"; cond = None };
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            ];
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        };
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      ];
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    configuration = None;
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  }
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