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Revision ca7ff3f7

Added by LĂ©lio Brun 8 months ago

reformatting

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src/tools/importer/vhdl_deriving_yojson.ml
1
let base_types = ["integer"; "character"; "bit"; "real"; "natural"; "positive"; "std_logic"; "std_logic_vector" ]
1
let base_types =
2
  [
3
    "integer";
4
    "character";
5
    "bit";
6
    "real";
7
    "natural";
8
    "positive";
9
    "std_logic";
10
    "std_logic_vector";
11
  ]
2 12

  
3 13
type vhdl_type_t =
4 14
  | Base of string
......
7 17
  | Array of int * int * vhdl_type_t
8 18
  | Enumerated of string list
9 19
  | Void
10
[@@deriving yojson];;
11
  
12
(************************************************************************************)		   
13
(*                     Constants                                                    *)
14
(************************************************************************************)		   
15

  
16
(* Std_logic values :
17
    'U': uninitialized. This signal hasn't been set yet.
18
    'X': unknown. Impossible to determine this value/result.
19
    '0': logic 0
20
    '1': logic 1
21
    'Z': High Impedance
22
    'W': Weak signal, can't tell if it should be 0 or 1.
23
    'L': Weak signal that should probably go to 0
24
    'H': Weak signal that should probably go to 1
25
    '-': Don't care. *)			       
26
let std_logic_cst = ["U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ]
27
let literal_base = ["B"; "O"; "X"; "UB"; "UO"; "UX"; "SB"; "SO"; "SX"; "D"] (* Prefix of CstLiteral *)
20
[@@deriving yojson]
21

  
22
(************************************************************************************)
23
(* Constants *)
24
(************************************************************************************)
25

  
26
(* Std_logic values : 'U': uninitialized. This signal hasn't been set yet. 'X':
27
   unknown. Impossible to determine this value/result. '0': logic 0 '1': logic 1
28
   'Z': High Impedance 'W': Weak signal, can't tell if it should be 0 or 1. 'L':
29
   Weak signal that should probably go to 0 'H': Weak signal that should
30
   probably go to 1 '-': Don't care. *)
31
let std_logic_cst = [ "U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ]
32

  
33
let literal_base = [ "B"; "O"; "X"; "UB"; "UO"; "UX"; "SB"; "SO"; "SX"; "D" ]
34
(* Prefix of CstLiteral *)
28 35

  
29 36
(* TODO: do we need more constructors ? *)
30
type cst_val_t = 
31
    CstInt of int 
37
type cst_val_t =
38
  | CstInt of int
32 39
  | CstStdLogic of string
33 40
  | CstLiteral of string [@name "CST_LITERAL"]
34
[@@deriving yojson {strict = false}];;
41
[@@deriving yojson { strict = false }]
35 42

  
36
type vhdl_subtype_indication_t =
37
  {
38
    name : string;
39
    definition: vhdl_type_t option [@default Some (Void)];
40
  }
41
[@@deriving yojson {strict = false}];;
43
type vhdl_subtype_indication_t = {
44
  name : string;
45
  definition : vhdl_type_t option; [@default Some Void]
46
}
47
[@@deriving yojson { strict = false }]
42 48

  
43
(* TODO ? Shall we merge definition / declaration  *)
49
(* TODO ? Shall we merge definition / declaration *)
44 50
type vhdl_definition_t =
45
  | Type of {name : string ; definition: vhdl_type_t} [@name "TYPE_DECLARATION"]
46
  | Subtype of {name : string ; typ : vhdl_subtype_indication_t} [@name "SUBTYPE_DECLARATION"]
47
[@@deriving yojson {strict = false}];;
48
					
51
  | Type of { name : string; definition : vhdl_type_t }
52
      [@name "TYPE_DECLARATION"]
53
  | Subtype of { name : string; typ : vhdl_subtype_indication_t }
54
      [@name "SUBTYPE_DECLARATION"]
55
[@@deriving yojson { strict = false }]
56

  
49 57
type vhdl_declaration_t =
50
  | VarDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "VARIABLE_DECLARATION"]
51
  | CstDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t  } [@name "CONSTANT_DECLARATION"]
52
  | SigDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "SIGNAL_DECLARATION"]
53
[@@deriving yojson {strict = false}];;
58
  | VarDecl of {
59
      names : string list;
60
      typ : vhdl_subtype_indication_t;
61
      init_val : cst_val_t option; [@default Some (CstInt 0)]
62
    } [@name "VARIABLE_DECLARATION"]
63
  | CstDecl of {
64
      names : string list;
65
      typ : vhdl_subtype_indication_t;
66
      init_val : cst_val_t;
67
    } [@name "CONSTANT_DECLARATION"]
68
  | SigDecl of {
69
      names : string list;
70
      typ : vhdl_subtype_indication_t;
71
      init_val : cst_val_t option; [@default Some (CstInt 0)]
72
    } [@name "SIGNAL_DECLARATION"]
73
[@@deriving yojson { strict = false }]
54 74

  
55
(************************************************************************************)		   
56
(*            Attributes for types, arrays, signals and strings                     *)
57
(************************************************************************************)		   
75
(************************************************************************************)
76
(* Attributes for types, arrays, signals and strings *)
77
(************************************************************************************)
58 78

  
59 79
type 'basetype vhdl_type_attributes_t =
60
  | TAttNoArg of { id: string }
61
  | TAttIntArg of { id: string; arg: int }
62
  | TAttValArg of { id: string; arg: 'basetype }
63
  | TAttStringArg of { id: string; arg: string }
64
[@@deriving yojson {strict = false}];;
65

  
66
let typ_att_noarg = ["base"; "left"; "right"; "high"; "low"]
67
let typ_att_intarg = ["pos"; "val"; "succ"; "pred"; "leftof"; "rightof"]
68
let typ_att_valarg = ["image"]
69
let typ_att_stringarg = ["value"]
70
  
71
type vhdl_array_attributes_t = AAttInt of { id: string; arg: int; } | AAttAscending
72
[@@deriving yojson {strict = false}];;
73

  
74
let array_att_intarg = ["left"; "right"; "high"; "low"; "range"; "reverse_range"; "length"]  
80
  | TAttNoArg of { id : string }
81
  | TAttIntArg of { id : string; arg : int }
82
  | TAttValArg of { id : string; arg : 'basetype }
83
  | TAttStringArg of { id : string; arg : string }
84
[@@deriving yojson { strict = false }]
85

  
86
let typ_att_noarg = [ "base"; "left"; "right"; "high"; "low" ]
87

  
88
let typ_att_intarg = [ "pos"; "val"; "succ"; "pred"; "leftof"; "rightof" ]
89

  
90
let typ_att_valarg = [ "image" ]
91

  
92
let typ_att_stringarg = [ "value" ]
93

  
94
type vhdl_array_attributes_t =
95
  | AAttInt of { id : string; arg : int }
96
  | AAttAscending
97
[@@deriving yojson { strict = false }]
98

  
99
let array_att_intarg =
100
  [ "left"; "right"; "high"; "low"; "range"; "reverse_range"; "length" ]
75 101

  
76 102
type vhdl_signal_attributes_t = SigAtt of string
77
[@@deriving yojson {strict = false}];;
103
[@@deriving yojson { strict = false }]
78 104

  
79 105
type vhdl_string_attributes_t = StringAtt of string
80
[@@deriving yojson {strict = false}];;
106
[@@deriving yojson { strict = false }]
81 107

  
82
(************************************************************************************)		   
83
(*                        Expressions  / Statements                                 *)
84
(************************************************************************************)		   
108
(************************************************************************************)
109
(* Expressions / Statements *)
110
(************************************************************************************)
85 111
type suffix_selection_t = Idx of int | Range of int * int
86
[@@deriving yojson {strict = false}];;
112
[@@deriving yojson { strict = false }]
87 113

  
88 114
type vhdl_expr_t =
89 115
  | Call of vhdl_name_t [@name "CALL"]
90 116
  | Cst of cst_val_t [@name "CONSTANT_VALUE"]
91
  | Op of { id: string [@default ""]; args: vhdl_expr_t list [@default []]} [@name "EXPRESSION"]
117
  | Op of { id : string; [@default ""] args : vhdl_expr_t list [@default []] }
118
      [@name "EXPRESSION"]
92 119
  | IsNull [@name "IsNull"]
93
  | Time of { value: int; phy_unit: string [@default ""]}
94
  | Sig of { name: string; att: vhdl_signal_attributes_t option }
120
  | Time of { value : int; phy_unit : string [@default ""] }
121
  | Sig of { name : string; att : vhdl_signal_attributes_t option }
95 122
  | SuffixMod of { expr : vhdl_expr_t; selection : suffix_selection_t }
96
[@@deriving yojson {strict = false}]
97
and					     
98
vhdl_name_t =
123
[@@deriving yojson { strict = false }]
124

  
125
and vhdl_name_t =
99 126
  | Simple of string [@name "SIMPLE_NAME"]
100 127
  | Selected of vhdl_name_t list [@name "SELECTED_NAME"]
101
  | Index of { id: vhdl_name_t; exprs: vhdl_expr_t list } [@name "INDEXED_NAME"]
102
  | Slice of { id: vhdl_name_t; range: vhdl_type_t } [@name "SLICE_NAME"]
103
  | Attribute of { id: vhdl_name_t; designator: vhdl_name_t; expr: vhdl_expr_t [@default IsNull]} [@name "ATTRIBUTE_NAME"]
104
  | Function of { id: vhdl_name_t; assoc_list: vhdl_assoc_element_t list } [@name "FUNCTION_CALL"]
128
  | Index of { id : vhdl_name_t; exprs : vhdl_expr_t list }
129
      [@name "INDEXED_NAME"]
130
  | Slice of { id : vhdl_name_t; range : vhdl_type_t } [@name "SLICE_NAME"]
131
  | Attribute of {
132
      id : vhdl_name_t;
133
      designator : vhdl_name_t;
134
      expr : vhdl_expr_t; [@default IsNull]
135
    } [@name "ATTRIBUTE_NAME"]
136
  | Function of { id : vhdl_name_t; assoc_list : vhdl_assoc_element_t list }
137
      [@name "FUNCTION_CALL"]
105 138
  | NoName
106
[@@deriving yojson {strict = false}]
107
and vhdl_assoc_element_t =
108
  {
109
    formal_name: vhdl_name_t option [@default Some NoName];
110
    formal_arg: vhdl_name_t option [@default Some NoName];
111
    actual_name: vhdl_name_t option [@default Some NoName];
112
    actual_designator: vhdl_name_t option [@default Some NoName];
113
    actual_expr: vhdl_expr_t option [@default Some IsNull];
114
  }
115
[@@deriving yojson {strict = false}];;
116

  
117
let arith_funs = ["+";"-";"*";"/";"mod"; "rem";"abs";"**";"&"]
118
let bool_funs  = ["and"; "or"; "nand"; "nor"; "xor"; "not"]
119
let rel_funs   = ["<";">";"<=";">=";"/=";"=";"?=";"?/=";"?<";"?<=";"?>";"?>=";"??"]
120
let shift_funs = ["sll";"srl";"sla";"sra";"rol";"ror"]
121

  
122
type vhdl_sequential_stmt_t = 
123
  | VarAssign of { lhs: vhdl_name_t; rhs: vhdl_expr_t }
124
  | SigSeqAssign of { label: string [@default ""]; lhs: vhdl_name_t; rhs: vhdl_expr_t list} [@name "SIGNAL_ASSIGNMENT_STATEMENT"]
125
  | If of { label: string [@default ""]; if_cases: vhdl_if_case_t list;
126
    default: vhdl_sequential_stmt_t list [@default []]; } [@name "IF_STATEMENT"]
127
  | Case of { guard: vhdl_expr_t; branches: vhdl_case_item_t list } [@name "CASE_STATEMENT_TREE"]
128
  | Exit of { label: string [@default ""]; loop_label: string option [@default Some ""]; condition: vhdl_expr_t option [@default Some IsNull]} [@name "EXIT_STATEMENT"]
129
  | Assert of { label: string [@default ""]; cond: vhdl_expr_t; report: vhdl_expr_t [@default IsNull]; severity: vhdl_expr_t [@default IsNull]} [@name "ASSERTION_STATEMENT"]
139
[@@deriving yojson { strict = false }]
140

  
141
and vhdl_assoc_element_t = {
142
  formal_name : vhdl_name_t option; [@default Some NoName]
143
  formal_arg : vhdl_name_t option; [@default Some NoName]
144
  actual_name : vhdl_name_t option; [@default Some NoName]
145
  actual_designator : vhdl_name_t option; [@default Some NoName]
146
  actual_expr : vhdl_expr_t option; [@default Some IsNull]
147
}
148
[@@deriving yojson { strict = false }]
149

  
150
let arith_funs = [ "+"; "-"; "*"; "/"; "mod"; "rem"; "abs"; "**"; "&" ]
151

  
152
let bool_funs = [ "and"; "or"; "nand"; "nor"; "xor"; "not" ]
153

  
154
let rel_funs =
155
  [
156
    "<"; ">"; "<="; ">="; "/="; "="; "?="; "?/="; "?<"; "?<="; "?>"; "?>="; "??";
157
  ]
158

  
159
let shift_funs = [ "sll"; "srl"; "sla"; "sra"; "rol"; "ror" ]
160

  
161
type vhdl_sequential_stmt_t =
162
  | VarAssign of { lhs : vhdl_name_t; rhs : vhdl_expr_t }
163
  | SigSeqAssign of {
164
      label : string; [@default ""]
165
      lhs : vhdl_name_t;
166
      rhs : vhdl_expr_t list;
167
    } [@name "SIGNAL_ASSIGNMENT_STATEMENT"]
168
  | If of {
169
      label : string; [@default ""]
170
      if_cases : vhdl_if_case_t list;
171
      default : vhdl_sequential_stmt_t list; [@default []]
172
    } [@name "IF_STATEMENT"]
173
  | Case of { guard : vhdl_expr_t; branches : vhdl_case_item_t list }
174
      [@name "CASE_STATEMENT_TREE"]
175
  | Exit of {
176
      label : string; [@default ""]
177
      loop_label : string option; [@default Some ""]
178
      condition : vhdl_expr_t option; [@default Some IsNull]
179
    } [@name "EXIT_STATEMENT"]
180
  | Assert of {
181
      label : string; [@default ""]
182
      cond : vhdl_expr_t;
183
      report : vhdl_expr_t; [@default IsNull]
184
      severity : vhdl_expr_t; [@default IsNull]
185
    } [@name "ASSERTION_STATEMENT"]
130 186
  | Wait [@name "WAIT_STATEMENT"]
131
  | Null of { label: string [@default ""]} [@name "NULL_STATEMENT"]
132
and vhdl_if_case_t = 
133
  {
134
    if_cond: vhdl_expr_t;
135
    if_block: vhdl_sequential_stmt_t list;
136
  }
137
and vhdl_case_item_t = 
138
  {
139
    when_cond: vhdl_expr_t list;
140
    when_stmt: vhdl_sequential_stmt_t list;
141
  }
142
[@@deriving yojson {strict = false}];;
143
				    
144
type signal_condition_t =
145
  {                            
146
    expr: vhdl_expr_t list;              (* when expression *)
147
    cond: vhdl_expr_t [@default IsNull];  (* optional else case expression. 
148
                                             If None, could be a latch  *)
149
  }
150
[@@deriving yojson {strict = false}];;
151

  
152
type signal_selection_t =
153
  {
154
    expr : vhdl_expr_t;
155
    when_sel: vhdl_expr_t list [@default []];
156
  }
157
[@@deriving yojson {strict = false}];;
158

  
159
type conditional_signal_t =
160
  {
161
    postponed: bool [@default false];
162
    label: string option [@default Some ""];
163
    lhs: vhdl_name_t;        (* assigned signal = target*)
164
    rhs: signal_condition_t list;                   (* expression *)
165
    cond: vhdl_expr_t [@default IsNull];
166
    delay: vhdl_expr_t [@default IsNull];
167
  }
168
[@@deriving yojson {strict = false}];;
169

  
170
type process_t =
171
  { 
172
    id: string option [@default Some ""];
173
    declarations: vhdl_declaration_t list option [@key "PROCESS_DECLARATIVE_PART"] [@default Some []];
174
    active_sigs: vhdl_name_t list [@default []];
175
    body: vhdl_sequential_stmt_t list [@key "PROCESS_STATEMENT_PART"] [@default []]
176
  }
177
[@@deriving yojson {strict = false}];;
178

  
179
type selected_signal_t = 
180
  { 
181
    postponed: bool [@default false];
182
    label: string option [@default Some ""];
183
    lhs: vhdl_name_t;      (* assigned signal = target *)
184
    sel: vhdl_expr_t;  
185
    branches: signal_selection_t list [@default []];
186
    delay: vhdl_expr_t option;
187
  }
188
[@@deriving yojson {strict = false}];;
189
			   
187
  | Null of { label : string [@default ""] } [@name "NULL_STATEMENT"]
188

  
189
and vhdl_if_case_t = {
190
  if_cond : vhdl_expr_t;
191
  if_block : vhdl_sequential_stmt_t list;
192
}
193

  
194
and vhdl_case_item_t = {
195
  when_cond : vhdl_expr_t list;
196
  when_stmt : vhdl_sequential_stmt_t list;
197
}
198
[@@deriving yojson { strict = false }]
199

  
200
type signal_condition_t = {
201
  expr : vhdl_expr_t list;
202
  (* when expression *)
203
  cond : vhdl_expr_t; [@default IsNull]
204
      (* optional else case expression. If None, could be a latch *)
205
}
206
[@@deriving yojson { strict = false }]
207

  
208
type signal_selection_t = {
209
  expr : vhdl_expr_t;
210
  when_sel : vhdl_expr_t list; [@default []]
211
}
212
[@@deriving yojson { strict = false }]
213

  
214
type conditional_signal_t = {
215
  postponed : bool; [@default false]
216
  label : string option; [@default Some ""]
217
  lhs : vhdl_name_t;
218
  (* assigned signal = target*)
219
  rhs : signal_condition_t list;
220
  (* expression *)
221
  cond : vhdl_expr_t; [@default IsNull]
222
  delay : vhdl_expr_t; [@default IsNull]
223
}
224
[@@deriving yojson { strict = false }]
225

  
226
type process_t = {
227
  id : string option; [@default Some ""]
228
  declarations : vhdl_declaration_t list option;
229
      [@key "PROCESS_DECLARATIVE_PART"] [@default Some []]
230
  active_sigs : vhdl_name_t list; [@default []]
231
  body : vhdl_sequential_stmt_t list;
232
      [@key "PROCESS_STATEMENT_PART"] [@default []]
233
}
234
[@@deriving yojson { strict = false }]
235

  
236
type selected_signal_t = {
237
  postponed : bool; [@default false]
238
  label : string option; [@default Some ""]
239
  lhs : vhdl_name_t;
240
  (* assigned signal = target *)
241
  sel : vhdl_expr_t;
242
  branches : signal_selection_t list; [@default []]
243
  delay : vhdl_expr_t option;
244
}
245
[@@deriving yojson { strict = false }]
246

  
190 247
type vhdl_concurrent_stmt_t =
191 248
  | SigAssign of conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
192 249
  | Process of process_t [@name "PROCESS_STATEMENT"]
193 250
  | SelectedSig of selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
194
[@@deriving yojson {strict = false}];;
195
  (*
196
type vhdl_statement_t =
197
  
198
  (* | DeclarationStmt of declaration_stmt_t *)
199
  | ConcurrentStmt of vhdl_concurrent_stmt_t
200
  | SequentialStmt of vhdl_sequential_stmt_t
201
   *)
202
		     
203
(************************************************************************************)		   
204
(*                     Entities                                                     *)
205
(************************************************************************************)		   
206
			     
251
[@@deriving yojson { strict = false }]
252

  
253
(* type vhdl_statement_t =
254

  
255
   (* | DeclarationStmt of declaration_stmt_t *) | ConcurrentStmt of
256
   vhdl_concurrent_stmt_t | SequentialStmt of vhdl_sequential_stmt_t *)
257

  
258
(************************************************************************************)
259
(* Entities *)
260
(************************************************************************************)
261

  
207 262
(* TODO? Seems to appear optionally in entities *)
208
type vhdl_generic_t = unit
209
[@@deriving yojson {strict = false}];;
210
			      
211
type vhdl_port_kind_t = 
212
    InPort     [@name "in"]
213
  | OutPort    [@name "out"]
214
  | InoutPort  [@name "inout"]
263
type vhdl_generic_t = unit [@@deriving yojson { strict = false }]
264

  
265
type vhdl_port_kind_t =
266
  | InPort [@name "in"]
267
  | OutPort [@name "out"]
268
  | InoutPort [@name "inout"]
215 269
  | BufferPort [@name "buffer"]
216
[@@deriving yojson];;
217
	     
218
type vhdl_port_t =
219
  {
220
    names: string list [@default []];
221
    kind: vhdl_port_kind_t;
222
    typ : string;
223
(*    typ: vhdl_type_t; *)
224
  }
225
[@@deriving yojson {strict = false}];;
226

  
227
type vhdl_entity_t =
228
  {
229
    name: string [@default ""];
230
    generics: vhdl_generic_t list option [@key "GENERIC_CLAUSE"] [@default Some []];
231
    ports: vhdl_port_t list [@key "PORT_CLAUSE"] [@default []];
232
  }
233
[@@deriving yojson {strict = false}];;
234

  
235
(************************************************************************************)		   
236
(*                    Packages / Library loading                                    *)
237
(************************************************************************************)		   
238
				
270
[@@deriving yojson]
271

  
272
type vhdl_port_t = {
273
  names : string list; [@default []]
274
  kind : vhdl_port_kind_t;
275
  typ : string; (* typ: vhdl_type_t; *)
276
}
277
[@@deriving yojson { strict = false }]
278

  
279
type vhdl_entity_t = {
280
  name : string; [@default ""]
281
  generics : vhdl_generic_t list option;
282
      [@key "GENERIC_CLAUSE"] [@default Some []]
283
  ports : vhdl_port_t list; [@key "PORT_CLAUSE"] [@default []]
284
}
285
[@@deriving yojson { strict = false }]
286

  
287
(************************************************************************************)
288
(* Packages / Library loading *)
289
(************************************************************************************)
290

  
239 291
(* Optional. Describes shared definitions *)
240
type vhdl_package_t =
241
  {
242
    name: string [@default ""];
243
    shared_defs: vhdl_definition_t list [@default []];
244
  }
245
[@@deriving yojson {strict = false}];;
246

  
247
type vhdl_load_t = 
248
    Library of string list [@name "LIBRARY_CLAUSE"] [@default ""]
292
type vhdl_package_t = {
293
  name : string; [@default ""]
294
  shared_defs : vhdl_definition_t list; [@default []]
295
}
296
[@@deriving yojson { strict = false }]
297

  
298
type vhdl_load_t =
299
  | Library of string list [@name "LIBRARY_CLAUSE"] [@default ""]
249 300
  | Use of string list [@name "USE_CLAUSE"] [@default []]
250
[@@deriving yojson];;
251

  
252
(************************************************************************************)		   
253
(*                        Architecture / VHDL Design                                *)
254
(************************************************************************************)		   
255
				       
256
type vhdl_architecture_t =
257
  {
258
    name: string [@default ""];
259
    entity: string [@default ""];
260
    declarations: vhdl_declaration_t list option [@key "ARCHITECTURE_DECLARATIVE_PART"] [@default Some []];
261
    body: vhdl_concurrent_stmt_t list option [@key "ARCHITECTURE_STATEMENT_PART"] [@default Some []]; 
262
  }
263
[@@deriving yojson {strict = false}];;
264
    
301
[@@deriving yojson]
302

  
303
(************************************************************************************)
304
(* Architecture / VHDL Design *)
305
(************************************************************************************)
306

  
307
type vhdl_architecture_t = {
308
  name : string; [@default ""]
309
  entity : string; [@default ""]
310
  declarations : vhdl_declaration_t list option;
311
      [@key "ARCHITECTURE_DECLARATIVE_PART"] [@default Some []]
312
  body : vhdl_concurrent_stmt_t list option;
313
      [@key "ARCHITECTURE_STATEMENT_PART"] [@default Some []]
314
}
315
[@@deriving yojson { strict = false }]
316

  
265 317
(* TODO. Configuration is optional *)
266
type vhdl_configuration_t = unit
267
[@@deriving yojson {strict = false}];;
268

  
269
type vhdl_design_t =
270
  {
271
    packages: vhdl_package_t list [@key "PACKAGE_DECLARATION"] [@default []];
272
    libraries: vhdl_load_t list option [@key "CONTEXT_CLAUSE"] [@default Some []];
273
    entities: vhdl_entity_t list [@key "ENTITY_DECLARATION"] [@default []];
274
    architectures: vhdl_architecture_t list [@key "ARCHITECTURE_BODY"] [@default []];
275
    configuration: vhdl_configuration_t option [@key "CONFIGURATION_DECLARATION"] [@default Some ()];
276
  }
277
[@@deriving yojson {strict = false}];;
278

  
279
type vhdl_design_file_t =
280
  {
281
    design_unit: vhdl_design_t list [@key "DESIGN_UNIT"] [@default []];
282
  }
283
[@@deriving yojson {strict = false}];;
284

  
285
type vhdl_file_t = 
286
  {
287
    design_file: vhdl_design_file_t [@key "DESIGN_FILE"];
288
  }
289
[@@deriving yojson];;
318
type vhdl_configuration_t = unit [@@deriving yojson { strict = false }]
319

  
320
type vhdl_design_t = {
321
  packages : vhdl_package_t list; [@key "PACKAGE_DECLARATION"] [@default []]
322
  libraries : vhdl_load_t list option;
323
      [@key "CONTEXT_CLAUSE"] [@default Some []]
324
  entities : vhdl_entity_t list; [@key "ENTITY_DECLARATION"] [@default []]
325
  architectures : vhdl_architecture_t list;
326
      [@key "ARCHITECTURE_BODY"] [@default []]
327
  configuration : vhdl_configuration_t option;
328
      [@key "CONFIGURATION_DECLARATION"] [@default Some ()]
329
}
330
[@@deriving yojson { strict = false }]
331

  
332
type vhdl_design_file_t = {
333
  design_unit : vhdl_design_t list; [@key "DESIGN_UNIT"] [@default []]
334
}
335
[@@deriving yojson { strict = false }]
336

  
337
type vhdl_file_t = { design_file : vhdl_design_file_t [@key "DESIGN_FILE"] }
338
[@@deriving yojson]

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