Revision ca7ff3f7
Added by Lélio Brun over 1 year ago
src/tools/importer/vhdl_deriving_yojson.ml | ||
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let base_types = ["integer"; "character"; "bit"; "real"; "natural"; "positive"; "std_logic"; "std_logic_vector" ] |
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let base_types = |
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[ |
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"integer"; |
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"character"; |
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"bit"; |
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"real"; |
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"natural"; |
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"positive"; |
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"std_logic"; |
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"std_logic_vector"; |
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] |
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type vhdl_type_t = |
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| Base of string |
... | ... | |
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| Array of int * int * vhdl_type_t |
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| Enumerated of string list |
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| Void |
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[@@deriving yojson];; |
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|
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(************************************************************************************) |
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(* Constants *) |
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(************************************************************************************) |
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(* Std_logic values : |
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'U': uninitialized. This signal hasn't been set yet. |
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'X': unknown. Impossible to determine this value/result. |
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'0': logic 0 |
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'1': logic 1 |
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'Z': High Impedance |
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'W': Weak signal, can't tell if it should be 0 or 1. |
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'L': Weak signal that should probably go to 0 |
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'H': Weak signal that should probably go to 1 |
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'-': Don't care. *) |
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let std_logic_cst = ["U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ] |
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let literal_base = ["B"; "O"; "X"; "UB"; "UO"; "UX"; "SB"; "SO"; "SX"; "D"] (* Prefix of CstLiteral *) |
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[@@deriving yojson] |
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|
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(************************************************************************************) |
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(* Constants *) |
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(************************************************************************************) |
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(* Std_logic values : 'U': uninitialized. This signal hasn't been set yet. 'X': |
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unknown. Impossible to determine this value/result. '0': logic 0 '1': logic 1 |
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'Z': High Impedance 'W': Weak signal, can't tell if it should be 0 or 1. 'L': |
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Weak signal that should probably go to 0 'H': Weak signal that should |
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probably go to 1 '-': Don't care. *) |
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let std_logic_cst = [ "U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ] |
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let literal_base = [ "B"; "O"; "X"; "UB"; "UO"; "UX"; "SB"; "SO"; "SX"; "D" ] |
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(* Prefix of CstLiteral *) |
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(* TODO: do we need more constructors ? *) |
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type cst_val_t =
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CstInt of int
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type cst_val_t = |
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| CstInt of int
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| CstStdLogic of string |
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| CstLiteral of string [@name "CST_LITERAL"] |
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[@@deriving yojson {strict = false}];;
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[@@deriving yojson { strict = false }]
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type vhdl_subtype_indication_t = |
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{ |
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name : string; |
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definition: vhdl_type_t option [@default Some (Void)]; |
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} |
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[@@deriving yojson {strict = false}];; |
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type vhdl_subtype_indication_t = { |
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name : string; |
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definition : vhdl_type_t option; [@default Some Void] |
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} |
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[@@deriving yojson { strict = false }] |
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(* TODO ? Shall we merge definition / declaration *)
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(* TODO ? Shall we merge definition / declaration *) |
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type vhdl_definition_t = |
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| Type of {name : string ; definition: vhdl_type_t} [@name "TYPE_DECLARATION"] |
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| Subtype of {name : string ; typ : vhdl_subtype_indication_t} [@name "SUBTYPE_DECLARATION"] |
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[@@deriving yojson {strict = false}];; |
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| Type of { name : string; definition : vhdl_type_t } |
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[@name "TYPE_DECLARATION"] |
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| Subtype of { name : string; typ : vhdl_subtype_indication_t } |
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[@name "SUBTYPE_DECLARATION"] |
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[@@deriving yojson { strict = false }] |
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type vhdl_declaration_t = |
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| VarDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "VARIABLE_DECLARATION"] |
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| CstDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t } [@name "CONSTANT_DECLARATION"] |
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| SigDecl of { names : string list; typ : vhdl_subtype_indication_t; init_val : cst_val_t option [@default Some (CstInt (0))] } [@name "SIGNAL_DECLARATION"] |
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[@@deriving yojson {strict = false}];; |
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| VarDecl of { |
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names : string list; |
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typ : vhdl_subtype_indication_t; |
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init_val : cst_val_t option; [@default Some (CstInt 0)] |
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} [@name "VARIABLE_DECLARATION"] |
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| CstDecl of { |
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names : string list; |
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typ : vhdl_subtype_indication_t; |
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init_val : cst_val_t; |
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} [@name "CONSTANT_DECLARATION"] |
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| SigDecl of { |
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names : string list; |
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typ : vhdl_subtype_indication_t; |
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init_val : cst_val_t option; [@default Some (CstInt 0)] |
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} [@name "SIGNAL_DECLARATION"] |
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[@@deriving yojson { strict = false }] |
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(************************************************************************************)
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(* Attributes for types, arrays, signals and strings *)
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(************************************************************************************)
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(************************************************************************************) |
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(* Attributes for types, arrays, signals and strings *)
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(************************************************************************************) |
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type 'basetype vhdl_type_attributes_t = |
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| TAttNoArg of { id: string } |
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| TAttIntArg of { id: string; arg: int } |
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| TAttValArg of { id: string; arg: 'basetype } |
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| TAttStringArg of { id: string; arg: string } |
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[@@deriving yojson {strict = false}];; |
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let typ_att_noarg = ["base"; "left"; "right"; "high"; "low"] |
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let typ_att_intarg = ["pos"; "val"; "succ"; "pred"; "leftof"; "rightof"] |
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let typ_att_valarg = ["image"] |
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let typ_att_stringarg = ["value"] |
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type vhdl_array_attributes_t = AAttInt of { id: string; arg: int; } | AAttAscending |
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[@@deriving yojson {strict = false}];; |
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let array_att_intarg = ["left"; "right"; "high"; "low"; "range"; "reverse_range"; "length"] |
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| TAttNoArg of { id : string } |
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| TAttIntArg of { id : string; arg : int } |
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| TAttValArg of { id : string; arg : 'basetype } |
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| TAttStringArg of { id : string; arg : string } |
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[@@deriving yojson { strict = false }] |
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let typ_att_noarg = [ "base"; "left"; "right"; "high"; "low" ] |
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let typ_att_intarg = [ "pos"; "val"; "succ"; "pred"; "leftof"; "rightof" ] |
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let typ_att_valarg = [ "image" ] |
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let typ_att_stringarg = [ "value" ] |
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type vhdl_array_attributes_t = |
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| AAttInt of { id : string; arg : int } |
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| AAttAscending |
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[@@deriving yojson { strict = false }] |
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let array_att_intarg = |
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[ "left"; "right"; "high"; "low"; "range"; "reverse_range"; "length" ] |
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type vhdl_signal_attributes_t = SigAtt of string |
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[@@deriving yojson {strict = false}];;
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[@@deriving yojson { strict = false }]
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type vhdl_string_attributes_t = StringAtt of string |
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[@@deriving yojson {strict = false}];;
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[@@deriving yojson { strict = false }]
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(************************************************************************************)
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(* Expressions / Statements *)
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(************************************************************************************)
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(************************************************************************************) |
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(* Expressions / Statements *)
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(************************************************************************************) |
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type suffix_selection_t = Idx of int | Range of int * int |
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[@@deriving yojson {strict = false}];;
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[@@deriving yojson { strict = false }]
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type vhdl_expr_t = |
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| Call of vhdl_name_t [@name "CALL"] |
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| Cst of cst_val_t [@name "CONSTANT_VALUE"] |
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| Op of { id: string [@default ""]; args: vhdl_expr_t list [@default []]} [@name "EXPRESSION"] |
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| Op of { id : string; [@default ""] args : vhdl_expr_t list [@default []] } |
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[@name "EXPRESSION"] |
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| IsNull [@name "IsNull"] |
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| Time of { value: int; phy_unit: string [@default ""]}
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| Sig of { name: string; att: vhdl_signal_attributes_t option }
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| Time of { value : int; phy_unit : string [@default ""] }
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| Sig of { name : string; att : vhdl_signal_attributes_t option }
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| SuffixMod of { expr : vhdl_expr_t; selection : suffix_selection_t } |
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[@@deriving yojson {strict = false}]
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and |
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vhdl_name_t = |
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[@@deriving yojson { strict = false }]
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and vhdl_name_t =
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| Simple of string [@name "SIMPLE_NAME"] |
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| Selected of vhdl_name_t list [@name "SELECTED_NAME"] |
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| Index of { id: vhdl_name_t; exprs: vhdl_expr_t list } [@name "INDEXED_NAME"] |
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| Slice of { id: vhdl_name_t; range: vhdl_type_t } [@name "SLICE_NAME"] |
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| Attribute of { id: vhdl_name_t; designator: vhdl_name_t; expr: vhdl_expr_t [@default IsNull]} [@name "ATTRIBUTE_NAME"] |
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| Function of { id: vhdl_name_t; assoc_list: vhdl_assoc_element_t list } [@name "FUNCTION_CALL"] |
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| Index of { id : vhdl_name_t; exprs : vhdl_expr_t list } |
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[@name "INDEXED_NAME"] |
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| Slice of { id : vhdl_name_t; range : vhdl_type_t } [@name "SLICE_NAME"] |
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| Attribute of { |
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id : vhdl_name_t; |
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designator : vhdl_name_t; |
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expr : vhdl_expr_t; [@default IsNull] |
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} [@name "ATTRIBUTE_NAME"] |
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| Function of { id : vhdl_name_t; assoc_list : vhdl_assoc_element_t list } |
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[@name "FUNCTION_CALL"] |
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| NoName |
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[@@deriving yojson {strict = false}] |
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and vhdl_assoc_element_t = |
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{ |
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formal_name: vhdl_name_t option [@default Some NoName]; |
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formal_arg: vhdl_name_t option [@default Some NoName]; |
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actual_name: vhdl_name_t option [@default Some NoName]; |
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actual_designator: vhdl_name_t option [@default Some NoName]; |
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actual_expr: vhdl_expr_t option [@default Some IsNull]; |
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} |
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[@@deriving yojson {strict = false}];; |
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let arith_funs = ["+";"-";"*";"/";"mod"; "rem";"abs";"**";"&"] |
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let bool_funs = ["and"; "or"; "nand"; "nor"; "xor"; "not"] |
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let rel_funs = ["<";">";"<=";">=";"/=";"=";"?=";"?/=";"?<";"?<=";"?>";"?>=";"??"] |
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let shift_funs = ["sll";"srl";"sla";"sra";"rol";"ror"] |
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type vhdl_sequential_stmt_t = |
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| VarAssign of { lhs: vhdl_name_t; rhs: vhdl_expr_t } |
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| SigSeqAssign of { label: string [@default ""]; lhs: vhdl_name_t; rhs: vhdl_expr_t list} [@name "SIGNAL_ASSIGNMENT_STATEMENT"] |
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| If of { label: string [@default ""]; if_cases: vhdl_if_case_t list; |
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default: vhdl_sequential_stmt_t list [@default []]; } [@name "IF_STATEMENT"] |
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| Case of { guard: vhdl_expr_t; branches: vhdl_case_item_t list } [@name "CASE_STATEMENT_TREE"] |
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| Exit of { label: string [@default ""]; loop_label: string option [@default Some ""]; condition: vhdl_expr_t option [@default Some IsNull]} [@name "EXIT_STATEMENT"] |
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| Assert of { label: string [@default ""]; cond: vhdl_expr_t; report: vhdl_expr_t [@default IsNull]; severity: vhdl_expr_t [@default IsNull]} [@name "ASSERTION_STATEMENT"] |
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[@@deriving yojson { strict = false }] |
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and vhdl_assoc_element_t = { |
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formal_name : vhdl_name_t option; [@default Some NoName] |
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formal_arg : vhdl_name_t option; [@default Some NoName] |
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actual_name : vhdl_name_t option; [@default Some NoName] |
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actual_designator : vhdl_name_t option; [@default Some NoName] |
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actual_expr : vhdl_expr_t option; [@default Some IsNull] |
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} |
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[@@deriving yojson { strict = false }] |
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let arith_funs = [ "+"; "-"; "*"; "/"; "mod"; "rem"; "abs"; "**"; "&" ] |
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let bool_funs = [ "and"; "or"; "nand"; "nor"; "xor"; "not" ] |
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|
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let rel_funs = |
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[ |
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"<"; ">"; "<="; ">="; "/="; "="; "?="; "?/="; "?<"; "?<="; "?>"; "?>="; "??"; |
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] |
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let shift_funs = [ "sll"; "srl"; "sla"; "sra"; "rol"; "ror" ] |
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type vhdl_sequential_stmt_t = |
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| VarAssign of { lhs : vhdl_name_t; rhs : vhdl_expr_t } |
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| SigSeqAssign of { |
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label : string; [@default ""] |
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lhs : vhdl_name_t; |
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rhs : vhdl_expr_t list; |
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} [@name "SIGNAL_ASSIGNMENT_STATEMENT"] |
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| If of { |
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label : string; [@default ""] |
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if_cases : vhdl_if_case_t list; |
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default : vhdl_sequential_stmt_t list; [@default []] |
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} [@name "IF_STATEMENT"] |
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| Case of { guard : vhdl_expr_t; branches : vhdl_case_item_t list } |
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[@name "CASE_STATEMENT_TREE"] |
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| Exit of { |
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label : string; [@default ""] |
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loop_label : string option; [@default Some ""] |
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condition : vhdl_expr_t option; [@default Some IsNull] |
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} [@name "EXIT_STATEMENT"] |
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| Assert of { |
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label : string; [@default ""] |
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cond : vhdl_expr_t; |
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report : vhdl_expr_t; [@default IsNull] |
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severity : vhdl_expr_t; [@default IsNull] |
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} [@name "ASSERTION_STATEMENT"] |
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| Wait [@name "WAIT_STATEMENT"] |
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| Null of { label: string [@default ""]} [@name "NULL_STATEMENT"] |
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and vhdl_if_case_t = |
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{ |
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if_cond: vhdl_expr_t; |
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if_block: vhdl_sequential_stmt_t list; |
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} |
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and vhdl_case_item_t = |
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{ |
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when_cond: vhdl_expr_t list; |
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when_stmt: vhdl_sequential_stmt_t list; |
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} |
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[@@deriving yojson {strict = false}];; |
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|
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type signal_condition_t = |
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{ |
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expr: vhdl_expr_t list; (* when expression *) |
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cond: vhdl_expr_t [@default IsNull]; (* optional else case expression. |
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If None, could be a latch *) |
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} |
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[@@deriving yojson {strict = false}];; |
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|
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type signal_selection_t = |
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{ |
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expr : vhdl_expr_t; |
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when_sel: vhdl_expr_t list [@default []]; |
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} |
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[@@deriving yojson {strict = false}];; |
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|
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159 |
type conditional_signal_t = |
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{ |
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postponed: bool [@default false]; |
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label: string option [@default Some ""]; |
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lhs: vhdl_name_t; (* assigned signal = target*) |
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rhs: signal_condition_t list; (* expression *) |
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cond: vhdl_expr_t [@default IsNull]; |
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delay: vhdl_expr_t [@default IsNull]; |
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} |
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[@@deriving yojson {strict = false}];; |
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|
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type process_t = |
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{ |
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id: string option [@default Some ""]; |
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declarations: vhdl_declaration_t list option [@key "PROCESS_DECLARATIVE_PART"] [@default Some []]; |
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active_sigs: vhdl_name_t list [@default []]; |
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body: vhdl_sequential_stmt_t list [@key "PROCESS_STATEMENT_PART"] [@default []] |
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} |
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[@@deriving yojson {strict = false}];; |
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|
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type selected_signal_t = |
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180 |
{ |
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postponed: bool [@default false]; |
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label: string option [@default Some ""]; |
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lhs: vhdl_name_t; (* assigned signal = target *) |
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sel: vhdl_expr_t; |
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branches: signal_selection_t list [@default []]; |
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delay: vhdl_expr_t option; |
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} |
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[@@deriving yojson {strict = false}];; |
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|
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| Null of { label : string [@default ""] } [@name "NULL_STATEMENT"] |
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|
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and vhdl_if_case_t = { |
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if_cond : vhdl_expr_t; |
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if_block : vhdl_sequential_stmt_t list; |
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} |
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|
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and vhdl_case_item_t = { |
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when_cond : vhdl_expr_t list; |
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when_stmt : vhdl_sequential_stmt_t list; |
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} |
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198 |
[@@deriving yojson { strict = false }] |
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199 |
|
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type signal_condition_t = { |
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expr : vhdl_expr_t list; |
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(* when expression *) |
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cond : vhdl_expr_t; [@default IsNull] |
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(* optional else case expression. If None, could be a latch *) |
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} |
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[@@deriving yojson { strict = false }] |
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207 |
|
|
208 |
type signal_selection_t = { |
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expr : vhdl_expr_t; |
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when_sel : vhdl_expr_t list; [@default []] |
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} |
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[@@deriving yojson { strict = false }] |
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|
|
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type conditional_signal_t = { |
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postponed : bool; [@default false] |
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label : string option; [@default Some ""] |
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lhs : vhdl_name_t; |
|
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(* assigned signal = target*) |
|
219 |
rhs : signal_condition_t list; |
|
220 |
(* expression *) |
|
221 |
cond : vhdl_expr_t; [@default IsNull] |
|
222 |
delay : vhdl_expr_t; [@default IsNull] |
|
223 |
} |
|
224 |
[@@deriving yojson { strict = false }] |
|
225 |
|
|
226 |
type process_t = { |
|
227 |
id : string option; [@default Some ""] |
|
228 |
declarations : vhdl_declaration_t list option; |
|
229 |
[@key "PROCESS_DECLARATIVE_PART"] [@default Some []] |
|
230 |
active_sigs : vhdl_name_t list; [@default []] |
|
231 |
body : vhdl_sequential_stmt_t list; |
|
232 |
[@key "PROCESS_STATEMENT_PART"] [@default []] |
|
233 |
} |
|
234 |
[@@deriving yojson { strict = false }] |
|
235 |
|
|
236 |
type selected_signal_t = { |
|
237 |
postponed : bool; [@default false] |
|
238 |
label : string option; [@default Some ""] |
|
239 |
lhs : vhdl_name_t; |
|
240 |
(* assigned signal = target *) |
|
241 |
sel : vhdl_expr_t; |
|
242 |
branches : signal_selection_t list; [@default []] |
|
243 |
delay : vhdl_expr_t option; |
|
244 |
} |
|
245 |
[@@deriving yojson { strict = false }] |
|
246 |
|
|
190 | 247 |
type vhdl_concurrent_stmt_t = |
191 | 248 |
| SigAssign of conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"] |
192 | 249 |
| Process of process_t [@name "PROCESS_STATEMENT"] |
193 | 250 |
| SelectedSig of selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"] |
194 |
[@@deriving yojson {strict = false}];; |
|
195 |
(* |
|
196 |
type vhdl_statement_t = |
|
197 |
|
|
198 |
(* | DeclarationStmt of declaration_stmt_t *) |
|
199 |
| ConcurrentStmt of vhdl_concurrent_stmt_t |
|
200 |
| SequentialStmt of vhdl_sequential_stmt_t |
|
201 |
*) |
|
202 |
|
|
203 |
(************************************************************************************) |
|
204 |
(* Entities *) |
|
205 |
(************************************************************************************) |
|
206 |
|
|
251 |
[@@deriving yojson { strict = false }] |
|
252 |
|
|
253 |
(* type vhdl_statement_t = |
|
254 |
|
|
255 |
(* | DeclarationStmt of declaration_stmt_t *) | ConcurrentStmt of |
|
256 |
vhdl_concurrent_stmt_t | SequentialStmt of vhdl_sequential_stmt_t *) |
|
257 |
|
|
258 |
(************************************************************************************) |
|
259 |
(* Entities *) |
|
260 |
(************************************************************************************) |
|
261 |
|
|
207 | 262 |
(* TODO? Seems to appear optionally in entities *) |
208 |
type vhdl_generic_t = unit |
|
209 |
[@@deriving yojson {strict = false}];; |
|
210 |
|
|
211 |
type vhdl_port_kind_t = |
|
212 |
InPort [@name "in"] |
|
213 |
| OutPort [@name "out"] |
|
214 |
| InoutPort [@name "inout"] |
|
263 |
type vhdl_generic_t = unit [@@deriving yojson { strict = false }] |
|
264 |
|
|
265 |
type vhdl_port_kind_t = |
|
266 |
| InPort [@name "in"] |
|
267 |
| OutPort [@name "out"] |
|
268 |
| InoutPort [@name "inout"] |
|
215 | 269 |
| BufferPort [@name "buffer"] |
216 |
[@@deriving yojson];; |
|
217 |
|
|
218 |
type vhdl_port_t = |
|
219 |
{ |
|
220 |
names: string list [@default []]; |
|
221 |
kind: vhdl_port_kind_t; |
|
222 |
typ : string; |
|
223 |
(* typ: vhdl_type_t; *) |
|
224 |
} |
|
225 |
[@@deriving yojson {strict = false}];; |
|
226 |
|
|
227 |
type vhdl_entity_t = |
|
228 |
{ |
|
229 |
name: string [@default ""]; |
|
230 |
generics: vhdl_generic_t list option [@key "GENERIC_CLAUSE"] [@default Some []]; |
|
231 |
ports: vhdl_port_t list [@key "PORT_CLAUSE"] [@default []]; |
|
232 |
} |
|
233 |
[@@deriving yojson {strict = false}];; |
|
234 |
|
|
235 |
(************************************************************************************) |
|
236 |
(* Packages / Library loading *) |
|
237 |
(************************************************************************************) |
|
238 |
|
|
270 |
[@@deriving yojson] |
|
271 |
|
|
272 |
type vhdl_port_t = { |
|
273 |
names : string list; [@default []] |
|
274 |
kind : vhdl_port_kind_t; |
|
275 |
typ : string; (* typ: vhdl_type_t; *) |
|
276 |
} |
|
277 |
[@@deriving yojson { strict = false }] |
|
278 |
|
|
279 |
type vhdl_entity_t = { |
|
280 |
name : string; [@default ""] |
|
281 |
generics : vhdl_generic_t list option; |
|
282 |
[@key "GENERIC_CLAUSE"] [@default Some []] |
|
283 |
ports : vhdl_port_t list; [@key "PORT_CLAUSE"] [@default []] |
|
284 |
} |
|
285 |
[@@deriving yojson { strict = false }] |
|
286 |
|
|
287 |
(************************************************************************************) |
|
288 |
(* Packages / Library loading *) |
|
289 |
(************************************************************************************) |
|
290 |
|
|
239 | 291 |
(* Optional. Describes shared definitions *) |
240 |
type vhdl_package_t = |
|
241 |
{ |
|
242 |
name: string [@default ""]; |
|
243 |
shared_defs: vhdl_definition_t list [@default []]; |
|
244 |
} |
|
245 |
[@@deriving yojson {strict = false}];; |
|
246 |
|
|
247 |
type vhdl_load_t = |
|
248 |
Library of string list [@name "LIBRARY_CLAUSE"] [@default ""] |
|
292 |
type vhdl_package_t = { |
|
293 |
name : string; [@default ""] |
|
294 |
shared_defs : vhdl_definition_t list; [@default []] |
|
295 |
} |
|
296 |
[@@deriving yojson { strict = false }] |
|
297 |
|
|
298 |
type vhdl_load_t = |
|
299 |
| Library of string list [@name "LIBRARY_CLAUSE"] [@default ""] |
|
249 | 300 |
| Use of string list [@name "USE_CLAUSE"] [@default []] |
250 |
[@@deriving yojson];; |
|
251 |
|
|
252 |
(************************************************************************************) |
|
253 |
(* Architecture / VHDL Design *) |
|
254 |
(************************************************************************************) |
|
255 |
|
|
256 |
type vhdl_architecture_t = |
|
257 |
{ |
|
258 |
name: string [@default ""]; |
|
259 |
entity: string [@default ""]; |
|
260 |
declarations: vhdl_declaration_t list option [@key "ARCHITECTURE_DECLARATIVE_PART"] [@default Some []]; |
|
261 |
body: vhdl_concurrent_stmt_t list option [@key "ARCHITECTURE_STATEMENT_PART"] [@default Some []]; |
|
262 |
} |
|
263 |
[@@deriving yojson {strict = false}];; |
|
264 |
|
|
301 |
[@@deriving yojson] |
|
302 |
|
|
303 |
(************************************************************************************) |
|
304 |
(* Architecture / VHDL Design *) |
|
305 |
(************************************************************************************) |
|
306 |
|
|
307 |
type vhdl_architecture_t = { |
|
308 |
name : string; [@default ""] |
|
309 |
entity : string; [@default ""] |
|
310 |
declarations : vhdl_declaration_t list option; |
|
311 |
[@key "ARCHITECTURE_DECLARATIVE_PART"] [@default Some []] |
|
312 |
body : vhdl_concurrent_stmt_t list option; |
|
313 |
[@key "ARCHITECTURE_STATEMENT_PART"] [@default Some []] |
|
314 |
} |
|
315 |
[@@deriving yojson { strict = false }] |
|
316 |
|
|
265 | 317 |
(* TODO. Configuration is optional *) |
266 |
type vhdl_configuration_t = unit |
|
267 |
[@@deriving yojson {strict = false}];; |
|
268 |
|
|
269 |
type vhdl_design_t = |
|
270 |
{ |
|
271 |
packages: vhdl_package_t list [@key "PACKAGE_DECLARATION"] [@default []]; |
|
272 |
libraries: vhdl_load_t list option [@key "CONTEXT_CLAUSE"] [@default Some []]; |
|
273 |
entities: vhdl_entity_t list [@key "ENTITY_DECLARATION"] [@default []]; |
|
274 |
architectures: vhdl_architecture_t list [@key "ARCHITECTURE_BODY"] [@default []]; |
|
275 |
configuration: vhdl_configuration_t option [@key "CONFIGURATION_DECLARATION"] [@default Some ()]; |
|
276 |
} |
|
277 |
[@@deriving yojson {strict = false}];; |
|
278 |
|
|
279 |
type vhdl_design_file_t = |
|
280 |
{ |
|
281 |
design_unit: vhdl_design_t list [@key "DESIGN_UNIT"] [@default []]; |
|
282 |
} |
|
283 |
[@@deriving yojson {strict = false}];; |
|
284 |
|
|
285 |
type vhdl_file_t = |
|
286 |
{ |
|
287 |
design_file: vhdl_design_file_t [@key "DESIGN_FILE"]; |
|
288 |
} |
|
289 |
[@@deriving yojson];; |
|
318 |
type vhdl_configuration_t = unit [@@deriving yojson { strict = false }] |
|
319 |
|
|
320 |
type vhdl_design_t = { |
|
321 |
packages : vhdl_package_t list; [@key "PACKAGE_DECLARATION"] [@default []] |
|
322 |
libraries : vhdl_load_t list option; |
|
323 |
[@key "CONTEXT_CLAUSE"] [@default Some []] |
|
324 |
entities : vhdl_entity_t list; [@key "ENTITY_DECLARATION"] [@default []] |
|
325 |
architectures : vhdl_architecture_t list; |
|
326 |
[@key "ARCHITECTURE_BODY"] [@default []] |
|
327 |
configuration : vhdl_configuration_t option; |
|
328 |
[@key "CONFIGURATION_DECLARATION"] [@default Some ()] |
|
329 |
} |
|
330 |
[@@deriving yojson { strict = false }] |
|
331 |
|
|
332 |
type vhdl_design_file_t = { |
|
333 |
design_unit : vhdl_design_t list; [@key "DESIGN_UNIT"] [@default []] |
|
334 |
} |
|
335 |
[@@deriving yojson { strict = false }] |
|
336 |
|
|
337 |
type vhdl_file_t = { design_file : vhdl_design_file_t [@key "DESIGN_FILE"] } |
|
338 |
[@@deriving yojson] |
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