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Revision ca7ff3f7

Added by LĂ©lio Brun 8 months ago

reformatting

View differences:

src/backends/VHDL/vhdl_test.ml
1 1
open Vhdl_ast
2 2

  
3
let design1 = {
4
    packages = [{name = "typedef"; shared_defs = [Subtype{name = "byte"; definition = Bit_vector (7, 0)}]}];
5
    libraries = [Use ["work";"typedef";"all"]];
6
    entities = [{ name = "data_path";
7
		  generics = [];
8
		  ports = [
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		      {name = "clk"; kind = InPort; typ = Base "boolean"};
10
		      {name = "rst"; kind = InPort; typ = Base "boolean"};
11
		      {name = "s_1"; kind = InPort; typ = Base "boolean"};
12
		      {name = "s0"; kind = InPort; typ = Base "bit"};
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		      {name = "s1"; kind = InPort; typ = Base "bit"};
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		      {name = "d0"; kind = InPort; typ = Base "byte"};
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		      {name = "d1"; kind = InPort; typ = Base "byte"};
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		      {name = "d2"; kind = InPort; typ = Base "byte"};
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		      {name = "d3"; kind = InPort; typ = Base "byte"};
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		      {name = "q"; kind = OutPort; typ = Base "byte"};
19
		      
20
		    ];
21
		}];
22
    architectures = [{
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			name = "behavior";
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			entity = "data_path";
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			declarations = [
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			    SigDecl { name = "reg"; typ = Base "byte"; init_val = None};
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			    SigDecl { name = "shft"; typ = Base "byte"; init_val = None};
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			    SigDecl { name = "sel"; typ = Bit_vector(1,0); init_val = None};
29

  
30
			  ];
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			body = [
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			    Process {
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				id = None;
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				active_sigs = ["clk"; "rst"];
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				body = [
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				    If {
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					if_cases = [
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					  {
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					    if_cond = Sig{ name = "rst"; att = None };
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					    if_block = [
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						SigSeqAssign { lhs = "req"; rhs = Cst (CstBV("x", "00"))};
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						SigSeqAssign { lhs = "shft"; rhs = Cst (CstBV("x", "00"))};
43
					      ];
44
					  };
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					  {
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					    if_cond = Op {id = "and"; args = [Sig{ name = "clk"; att = None };
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									      Sig{ name = "clk"; att = Some (SigAtt "event") }]};
48
					    if_block = [
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						SigSeqAssign { lhs = "req"; rhs = Op { id = "&"; args = [
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											   Sig{ name = "s0"; att = None };
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											   Sig{ name = "s1"; att = None }
52
											 ]
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										     }
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							     };
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						Case {
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						    guard = Sig{ name = "sel"; att = None };
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						    branches = [
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							{
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							  when_cond = Cst (CstBV("b", "00"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d0"; att = None }};
61
							};
62
							{
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							  when_cond = Cst (CstBV("b", "10"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d1"; att = None }};
65
							};
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							{
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							  when_cond = Cst (CstBV("b", "01"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d2"; att = None }};
69
							};
70
							{
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							  when_cond = Cst (CstBV("b", "11"));
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							  when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d3"; att = None }};
73
							};
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						      ]
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						  };
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						If {
79
						    if_cases = [
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						      {
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							if_cond = Sig{ name = "s_1"; att = None };
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							if_block = [
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							    SigSeqAssign {
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								lhs = "shft";
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								rhs = Op { id = "&";
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									   args = [
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									       SuffixMod {
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										   expr = Sig{ name = "shft"; att = None };
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										   selection = Range (6,0);
90
										 };
91
									       SuffixMod {
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										   expr = Sig{ name = "shft"; att = None };
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										   selection = Idx 7;
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										 }
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									     ]
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									 }
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							      };
98
							  ];
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						      };
100
						    ];
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						    default = Some [
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								  SigSeqAssign { lhs = "shft"; rhs = Var "reg"};
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								]
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						  };
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					      ];
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					  };
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					];
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					default = None;
110
				      }
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				  ];
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			      };
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			    SigAssign {
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				lhs = "q";
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				rhs = Var "shft";
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				cond = None;
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			      }
118

  
119
			  ];
120
		      }];
3
let design1 =
4
  {
5
    packages =
6
      [
7
        {
8
          name = "typedef";
9
          shared_defs =
10
            [ Subtype { name = "byte"; definition = Bit_vector (7, 0) } ];
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        };
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      ];
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    libraries = [ Use [ "work"; "typedef"; "all" ] ];
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    entities =
15
      [
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        {
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          name = "data_path";
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          generics = [];
19
          ports =
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            [
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              { name = "clk"; kind = InPort; typ = Base "boolean" };
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              { name = "rst"; kind = InPort; typ = Base "boolean" };
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              { name = "s_1"; kind = InPort; typ = Base "boolean" };
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              { name = "s0"; kind = InPort; typ = Base "bit" };
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              { name = "s1"; kind = InPort; typ = Base "bit" };
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              { name = "d0"; kind = InPort; typ = Base "byte" };
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              { name = "d1"; kind = InPort; typ = Base "byte" };
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              { name = "d2"; kind = InPort; typ = Base "byte" };
29
              { name = "d3"; kind = InPort; typ = Base "byte" };
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              { name = "q"; kind = OutPort; typ = Base "byte" };
31
            ];
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        };
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      ];
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    architectures =
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      [
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        {
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          name = "behavior";
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          entity = "data_path";
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          declarations =
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            [
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              SigDecl { name = "reg"; typ = Base "byte"; init_val = None };
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              SigDecl { name = "shft"; typ = Base "byte"; init_val = None };
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              SigDecl { name = "sel"; typ = Bit_vector (1, 0); init_val = None };
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            ];
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          body =
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            [
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              Process
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                {
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                  id = None;
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                  active_sigs = [ "clk"; "rst" ];
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                  body =
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                    [
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                      If
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                        {
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                          if_cases =
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                            [
57
                              {
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                                if_cond = Sig { name = "rst"; att = None };
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                                if_block =
60
                                  [
61
                                    SigSeqAssign
62
                                      {
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                                        lhs = "req";
64
                                        rhs = Cst (CstBV ("x", "00"));
65
                                      };
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                                    SigSeqAssign
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                                      {
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                                        lhs = "shft";
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                                        rhs = Cst (CstBV ("x", "00"));
70
                                      };
71
                                  ];
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                              };
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                              {
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                                if_cond =
75
                                  Op
76
                                    {
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                                      id = "and";
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                                      args =
79
                                        [
80
                                          Sig { name = "clk"; att = None };
81
                                          Sig
82
                                            {
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                                              name = "clk";
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                                              att = Some (SigAtt "event");
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                                            };
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                                        ];
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                                    };
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                                if_block =
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                                  [
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                                    SigSeqAssign
91
                                      {
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                                        lhs = "req";
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                                        rhs =
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                                          Op
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                                            {
96
                                              id = "&";
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                                              args =
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                                                [
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                                                  Sig
100
                                                    { name = "s0"; att = None };
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                                                  Sig
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                                                    { name = "s1"; att = None };
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                                                ];
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                                            };
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                                      };
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                                    Case
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                                      {
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                                        guard = Sig { name = "sel"; att = None };
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                                        branches =
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                                          [
111
                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "00"));
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                                              when_stmt =
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                                                SigSeqAssign
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                                                  {
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                                                    lhs = "req";
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                                                    rhs =
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                                                      Sig
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                                                        {
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                                                          name = "d0";
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                                                          att = None;
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                                                        };
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                                                  };
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                                            };
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                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "10"));
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                                              when_stmt =
130
                                                SigSeqAssign
131
                                                  {
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                                                    lhs = "req";
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                                                    rhs =
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                                                      Sig
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                                                        {
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                                                          name = "d1";
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                                                          att = None;
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                                                        };
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                                                  };
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                                            };
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                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "01"));
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                                              when_stmt =
145
                                                SigSeqAssign
146
                                                  {
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                                                    lhs = "req";
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                                                    rhs =
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                                                      Sig
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                                                        {
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                                                          name = "d2";
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                                                          att = None;
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                                                        };
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                                                  };
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                                            };
156
                                            {
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                                              when_cond =
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                                                Cst (CstBV ("b", "11"));
159
                                              when_stmt =
160
                                                SigSeqAssign
161
                                                  {
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                                                    lhs = "req";
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                                                    rhs =
164
                                                      Sig
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                                                        {
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                                                          name = "d3";
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                                                          att = None;
168
                                                        };
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                                                  };
170
                                            };
171
                                          ];
172
                                      };
173
                                    If
174
                                      {
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                                        if_cases =
176
                                          [
177
                                            {
178
                                              if_cond =
179
                                                Sig { name = "s_1"; att = None };
180
                                              if_block =
181
                                                [
182
                                                  SigSeqAssign
183
                                                    {
184
                                                      lhs = "shft";
185
                                                      rhs =
186
                                                        Op
187
                                                          {
188
                                                            id = "&";
189
                                                            args =
190
                                                              [
191
                                                                SuffixMod
192
                                                                  {
193
                                                                    expr =
194
                                                                      Sig
195
                                                                        {
196
                                                                          name =
197
                                                                            "shft";
198
                                                                          att =
199
                                                                            None;
200
                                                                        };
201
                                                                    selection =
202
                                                                      Range
203
                                                                        (6, 0);
204
                                                                  };
205
                                                                SuffixMod
206
                                                                  {
207
                                                                    expr =
208
                                                                      Sig
209
                                                                        {
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                                                                          name =
211
                                                                            "shft";
212
                                                                          att =
213
                                                                            None;
214
                                                                        };
215
                                                                    selection =
216
                                                                      Idx 7;
217
                                                                  };
218
                                                              ];
219
                                                          };
220
                                                    };
221
                                                ];
222
                                            };
223
                                          ];
224
                                        default =
225
                                          Some
226
                                            [
227
                                              SigSeqAssign
228
                                                {
229
                                                  lhs = "shft";
230
                                                  rhs = Var "reg";
231
                                                };
232
                                            ];
233
                                      };
234
                                  ];
235
                              };
236
                            ];
237
                          default = None;
238
                        };
239
                    ];
240
                };
241
              SigAssign { lhs = "q"; rhs = Var "shft"; cond = None };
242
            ];
243
        };
244
      ];
121 245
    configuration = None;
122 246
  }
123
  

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