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(* source: Synario VHDL Reference Manual - March 1997 *)
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(************************************************************************************)
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(* Types *)
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(************************************************************************************)
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let base_types =
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  [
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    "integer";
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    "character";
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    "bit";
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    "real";
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    "natural";
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    "positive";
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    "std_logic";
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    "std_logic_vector";
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  ]
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type vhdl_type_t =
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  | Base of string
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  | Range of string option * int * int
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  | Bit_vector of int * int
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  | Array of int * int * vhdl_type_t
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  | Enumerated of string list
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let rec pp_vhdl_type fmt t =
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  match t with
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  | Base s ->
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    Format.fprintf fmt "%s" s
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  | Bit_vector (n, m) ->
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    Format.fprintf fmt "bit_vector(%i downto %i)" n m
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  | Range (base, n, m) ->
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    Format.fprintf fmt "%trange %i to %i"
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      (fun fmt ->
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        match base with Some s -> Format.fprintf fmt "%s " s | None -> ())
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      n m
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  | Array (n, m, base) ->
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    Format.fprintf fmt "array (%i to %i) of %a" n m pp_vhdl_type base
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  | Enumerated sl ->
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    Format.fprintf fmt "(%a)"
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      (Utils.fprintf_list ~sep:", " Format.pp_print_string)
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      sl
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(************************************************************************************)
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(* Constants *)
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(************************************************************************************)
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(* Std_logic values : 'U': uninitialized. This signal hasn't been set yet. 'X':
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   unknown. Impossible to determine this value/result. '0': logic 0 '1': logic 1
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   'Z': High Impedance 'W': Weak signal, can't tell if it should be 0 or 1. 'L':
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   Weak signal that should probably go to 0 'H': Weak signal that should
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   probably go to 1 '-': Don't care. *)
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let std_logic_cst = [ "U"; "X"; "0"; "1"; "Z"; "W"; "L"; "H"; "-" ]
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(* TODO: do we need more constructors ? *)
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type cst_val_t =
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  | CstInt of int
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  | CstStdLogic of string
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  | CstBV of string * string
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let pp_cst_val fmt c =
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  match c with
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  | CstInt i ->
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    Format.fprintf fmt "%i" i
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  | CstStdLogic s ->
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    if List.mem s std_logic_cst then Format.fprintf fmt "%s" s else assert false
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  | CstBV (pref, suff) ->
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    Format.fprintf fmt "%s\"%s\"" pref suff
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(************************************************************************************)
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(* Declarations *)
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(************************************************************************************)
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(* TODO ? Shall we merge definition / declaration ? Do they appear at the same
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   place or at different ones ? *)
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type vhdl_definition_t =
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  | Type of { name : string; definition : vhdl_type_t }
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  | Subtype of { name : string; definition : vhdl_type_t }
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let pp_vhdl_definition fmt def =
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  match def with
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  | Type s ->
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    Format.fprintf fmt "type %s is %a;" s.name pp_vhdl_type s.definition
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  | Subtype s ->
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    Format.fprintf fmt "subtype %s is %a;" s.name pp_vhdl_type s.definition
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type vhdl_declaration_t =
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  | VarDecl of { name : string; typ : vhdl_type_t; init_val : cst_val_t option }
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  | CstDecl of { name : string; typ : vhdl_type_t; init_val : cst_val_t }
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  | SigDecl of { name : string; typ : vhdl_type_t; init_val : cst_val_t option }
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let pp_vhdl_declaration fmt decl =
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  match decl with
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  | VarDecl v ->
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    Format.fprintf fmt "variable %s : %a%t;" v.name pp_vhdl_type v.typ
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      (fun fmt ->
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        match v.init_val with
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        | Some initv ->
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          Format.fprintf fmt " := %a" pp_cst_val initv
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        | _ ->
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          ())
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  | CstDecl v ->
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    Format.fprintf fmt "constant %s : %a := %a;" v.name pp_vhdl_type v.typ
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      pp_cst_val v.init_val
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  | SigDecl v ->
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    Format.fprintf fmt "signal %s : %a%t;" v.name pp_vhdl_type v.typ (fun fmt ->
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        match v.init_val with
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        | Some initv ->
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          Format.fprintf fmt " := %a" pp_cst_val initv
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        | _ ->
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          ())
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(************************************************************************************)
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(* Attributes for types, arrays, signals and strings *)
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(************************************************************************************)
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type 'basetype vhdl_type_attributes_t =
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  | TAttNoArg of { id : string }
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  | TAttIntArg of { id : string; arg : int }
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  | TAttValArg of { id : string; arg : 'basetype }
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  | TAttStringArg of { id : string; arg : string }
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let typ_att_noarg = [ "base"; "left"; "right"; "high"; "low" ]
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let typ_att_intarg = [ "pos"; "val"; "succ"; "pred"; "leftof"; "rightof" ]
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let typ_att_valarg = [ "image" ]
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let typ_att_stringarg = [ "value" ]
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let pp_type_attribute pp_val fmt tatt =
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  match tatt with
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  | TAttNoArg a ->
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    Format.fprintf fmt "'%s" a.id
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  | TAttIntArg a ->
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    Format.fprintf fmt "'%s(%i)" a.id a.arg
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  | TAttValArg a ->
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    Format.fprintf fmt "'%s(%a)" a.id pp_val a.arg
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  | TAttStringArg a ->
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    Format.fprintf fmt "'%s(%s)" a.id a.arg
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type vhdl_array_attributes_t =
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  | AAttInt of { id : string; arg : int }
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  | AAttAscending
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let pp_array_attribute fmt aatt =
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  match aatt with
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  | AAttInt a ->
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    Format.fprintf fmt "'%s(%i)" a.id a.arg
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  | AAttAscending ->
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    Format.fprintf fmt "'ascending"
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let array_att_intarg =
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  [ "left"; "right"; "high"; "low"; "range"; "reverse_range"; "length" ]
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type vhdl_signal_attributes_t = SigAtt of string
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let pp_signal_attribute fmt sa =
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  match sa with SigAtt s -> Format.fprintf fmt "'%s" s
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let signal_att = [ "event"; "stable"; "last_value" ]
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type vhdl_string_attributes_t = StringAtt of string
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let pp_string_attribute fmt sa =
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  match sa with StringAtt s -> Format.fprintf fmt "'%s" s
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let signal_att = [ "simple_name"; "path_name"; "instance_name" ]
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(************************************************************************************)
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(* Expressions / Statements *)
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(************************************************************************************)
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(* TODO: call to functions? procedures? component instanciations ? *)
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type suffix_selection_t = Idx of int | Range of int * int
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let pp_suffix_selection fmt sel =
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  match sel with
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  | Idx n ->
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    Format.fprintf fmt "(%i)" n
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  | Range (n, m) ->
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    Format.fprintf fmt "(%i downto %i)" n m
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type vhdl_expr_t =
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  | Cst of cst_val_t
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  | Var of string
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  (* a signal or a variable *)
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  | Sig of { name : string; att : vhdl_signal_attributes_t option }
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  | SuffixMod of { expr : vhdl_expr_t; selection : suffix_selection_t }
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  | Op of { id : string; args : vhdl_expr_t list }
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let rec pp_vhdl_expr fmt e =
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  match e with
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  | Cst c ->
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    pp_cst_val fmt c
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  | Var s ->
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    Format.fprintf fmt "%s" s
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  | Sig s ->
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    Format.fprintf fmt "%s%t" s.name (fun fmt ->
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        match s.att with None -> () | Some att -> pp_signal_attribute fmt att)
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  | SuffixMod s ->
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    Format.fprintf fmt "%a %a" pp_vhdl_expr s.expr pp_suffix_selection
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      s.selection
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  | Op op -> (
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    match op.args with
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    | [] ->
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      assert false
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    | [ e1; e2 ] ->
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      Format.fprintf fmt "@[<hov 3>%a %s %a@]" pp_vhdl_expr e1 op.id
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        pp_vhdl_expr e2
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    | _ ->
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      assert false
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      (* all ops are binary up to now *)
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      (* | _ -> Format.fprintf fmt "@[<hov 3>%s (%a)@]" op.id
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         (Utils.fprintf_list ~sep:",@ " pp_vhdl_expr) op.args *))
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(* Available operators in the standard library. There are some restrictions on
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   types. See reference doc. *)
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let arith_funs = [ "+"; "-"; "*"; "/"; "mod"; "rem"; "abs"; "**" ]
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let bool_funs = [ "and"; "or"; "nand"; "nor"; "xor"; "not" ]
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let rel_funs = [ "<"; ">"; "<="; ">="; "/="; "=" ]
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type vhdl_if_case_t = {
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  if_cond : vhdl_expr_t;
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  if_block : vhdl_sequential_stmt_t list;
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}
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and vhdl_sequential_stmt_t =
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  | VarAssign of { lhs : string; rhs : vhdl_expr_t }
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  | SigSeqAssign of { lhs : string; rhs : vhdl_expr_t }
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  | If of {
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      if_cases : vhdl_if_case_t list;
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      default : vhdl_sequential_stmt_t list option;
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    }
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  | Case of { guard : vhdl_expr_t; branches : vhdl_case_item_t list }
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and vhdl_case_item_t = {
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  when_cond : vhdl_expr_t;
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  when_stmt : vhdl_sequential_stmt_t;
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}
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let rec pp_vhdl_sequential_stmt fmt stmt =
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  match stmt with
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  | VarAssign va ->
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    Format.fprintf fmt "%s := %a;" va.lhs pp_vhdl_expr va.rhs
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  | SigSeqAssign va ->
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    Format.fprintf fmt "%s <= %a;" va.lhs pp_vhdl_expr va.rhs
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  | If ifva ->
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    List.iteri
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      (fun idx ifcase ->
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        if idx = 0 then Format.fprintf fmt "@[<v 3>if"
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        else Format.fprintf fmt "@ @[<v 3>elsif";
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        Format.fprintf fmt " %a then@ %a@]" pp_vhdl_expr ifcase.if_cond
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          pp_vhdl_sequential_stmts ifcase.if_block)
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      ifva.if_cases;
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    let _ =
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      match ifva.default with
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      | None ->
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        ()
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      | Some bl ->
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        Format.fprintf fmt "@ @[<v 3>else@ %a@]" pp_vhdl_sequential_stmts bl
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    in
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    Format.fprintf fmt "@ end if;"
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  | Case caseva ->
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    Format.fprintf fmt "@[<v 3>case %a is@ %a@]@ end case;" pp_vhdl_expr
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      caseva.guard
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      (Utils.fprintf_list ~sep:"@ " pp_vhdl_case)
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      caseva.branches
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and pp_vhdl_sequential_stmts fmt l =
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  Utils.fprintf_list ~sep:"@ " pp_vhdl_sequential_stmt fmt l
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and pp_vhdl_case fmt case =
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  Format.fprintf fmt "when %a => %a" pp_vhdl_expr case.when_cond
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    pp_vhdl_sequential_stmt case.when_stmt
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type signal_condition_t = {
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  expr : vhdl_expr_t;
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  (* when expression *)
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  else_case : vhdl_expr_t option;
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      (* optional else case expression. If None, could be a latch *)
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}
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type signal_selection_t = {
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  sel_lhs : string;
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  expr : vhdl_expr_t;
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  when_sel : vhdl_expr_t option;
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}
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type conditional_signal_t = {
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  lhs : string;
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  (* assigned signal *)
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  rhs : vhdl_expr_t;
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  (* expression *)
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  cond : signal_condition_t option; (* conditional signal statement *)
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}
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type process_t = {
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  id : string option;
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  active_sigs : string list;
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  body : vhdl_sequential_stmt_t list;
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}
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type selected_signal_t = {
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  sel : vhdl_expr_t;
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  branches : signal_selection_t list;
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}
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type vhdl_concurrent_stmt_t =
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  | SigAssign of conditional_signal_t
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  | Process of process_t
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  | SelectedSig of selected_signal_t
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(* type vhdl_statement_t =
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   (* | DeclarationStmt of declaration_stmt_t *) | ConcurrentStmt of
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   vhdl_concurrent_stmt_t | SequentialStmt of vhdl_sequential_stmt_t *)
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let pp_vhdl_concurrent_stmt fmt stmt =
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  let pp_sig_cond fmt va =
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    Format.fprintf fmt "%s <= %a%t;" va.lhs pp_vhdl_expr va.rhs (fun fmt ->
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        match va.cond with
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        | None ->
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          ()
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        | Some cond ->
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          Format.fprintf fmt " when %a%t" pp_vhdl_expr cond.expr (fun fmt ->
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              match cond.else_case with
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              | None ->
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                ()
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              | Some else_case ->
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                Format.fprintf fmt " else %a" pp_vhdl_expr else_case))
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  in
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  let pp_process fmt p =
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    Format.fprintf fmt "@[<v 0>%tprocess %a@ @[<v 3>begin@ %a@]@ end process;@]"
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      (fun fmt ->
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        match p.id with Some id -> Format.fprintf fmt "%s: " id | None -> ())
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      (fun fmt asigs ->
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        if asigs <> [] then
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          Format.fprintf fmt "(@[<hov 0>%a)@]"
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            (Utils.fprintf_list ~sep:",@ " Format.pp_print_string)
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            asigs)
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      p.active_sigs
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      (Utils.fprintf_list ~sep:"@ " pp_vhdl_sequential_stmt)
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      p.body
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  in
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  let pp_sig_sel fmt va =
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    Format.fprintf fmt "@[<v 3>with %a select@ %a;@]" pp_vhdl_expr va.sel
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      (Utils.fprintf_list ~sep:"@ " (fun fmt b ->
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           Format.fprintf fmt "%s <= %a when %t" b.sel_lhs pp_vhdl_expr b.expr
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             (fun fmt ->
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               match b.when_sel with
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               | None ->
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                 Format.fprintf fmt "others"
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               | Some w ->
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                 pp_vhdl_expr fmt w)))
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      va.branches
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  in
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  match stmt with
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  | SigAssign va ->
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    pp_sig_cond fmt va
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  | Process p ->
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    pp_process fmt p
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  | SelectedSig va ->
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    pp_sig_sel fmt va
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(************************************************************************************)
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(* Entities *)
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(************************************************************************************)
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(* TODO? Seems to appear optionally in entities *)
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type vhdl_generic_t = unit
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let pp_vhdl_generic fmt g = ()
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type vhdl_port_kind_t = InPort | OutPort | InoutPort | BufferPort
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let pp_vhdl_port_kind fmt p =
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  match p with
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  | InPort ->
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    Format.fprintf fmt "in"
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  | OutPort ->
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    Format.fprintf fmt "in"
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  | InoutPort ->
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    Format.fprintf fmt "inout"
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  | BufferPort ->
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    Format.fprintf fmt "buffer"
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type vhdl_port_t = { name : string; kind : vhdl_port_kind_t; typ : vhdl_type_t }
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let pp_vhdl_port fmt p =
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  Format.fprintf fmt "%s : %a %a" p.name pp_vhdl_port_kind p.kind pp_vhdl_type
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    p.typ
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type vhdl_entity_t = {
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  name : string;
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  generics : vhdl_generic_t list;
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  ports : vhdl_port_t list;
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}
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let pp_vhdl_entity fmt e =
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  Format.fprintf fmt "@[<v 3>entity %s is@ %t%t@]@ end %s;@ " e.name
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    (fun fmt ->
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      List.iter
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        (fun g -> Format.fprintf fmt "generic %a;@ " pp_vhdl_generic g)
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        e.generics)
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    (fun fmt ->
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      if e.ports = [] then ()
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      else
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        Format.fprintf fmt "port (@[<hov 0>%a@]);"
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          (Utils.fprintf_list ~sep:",@ " pp_vhdl_port)
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          e.ports)
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    e.name
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(************************************************************************************)
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(* Packages / Library loading *)
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(************************************************************************************)
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(* Optional. Describes shared definitions *)
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type vhdl_package_t = { name : string; shared_defs : vhdl_definition_t list }
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let pp_vhdl_package fmt p =
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  Format.fprintf fmt "@[<v 3>package %s is@ %a@]@ end %s;@ " p.name
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    (Utils.fprintf_list ~sep:"@ " pp_vhdl_definition)
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    p.shared_defs p.name
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type vhdl_load_t = Library of string | Use of string list
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let pp_vhdl_load fmt l =
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  match l with
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  | Library s ->
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    Format.fprintf fmt "library %s;@ " s
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  | Use sl ->
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    Format.fprintf fmt "use %a;@ "
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      (Utils.fprintf_list ~sep:"." Format.pp_print_string)
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      sl
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(************************************************************************************)
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(* Architecture / VHDL Design *)
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(************************************************************************************)
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type vhdl_architecture_t = {
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  name : string;
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  entity : string;
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  declarations : vhdl_declaration_t list;
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  body : vhdl_concurrent_stmt_t list;
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}
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let pp_vhdl_architecture fmt a =
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  Format.fprintf fmt
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    "@[<v 3>architecture %s of %s is@ %a@]@ @[<v 3>begin@ %a@]@ end %s;" a.name
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    a.entity
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    (Utils.fprintf_list ~sep:"@ " pp_vhdl_declaration)
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    a.declarations
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    (Utils.fprintf_list ~sep:"@ " pp_vhdl_concurrent_stmt)
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    a.body a.name
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(* TODO. Configuraiton is optional *)
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type vhdl_configuration_t = unit
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let pp_vhdl_configuration fmt c = ()
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type vhdl_design_t = {
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  packages : vhdl_package_t list;
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  libraries : vhdl_load_t list;
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  entities : vhdl_entity_t list;
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  architectures : vhdl_architecture_t list;
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  configuration : vhdl_configuration_t option;
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}
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let pp_vhdl_design fmt d =
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  Format.fprintf fmt "@[<v 0>%a%t%a%t%a%t%a%t@]"
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    (Utils.fprintf_list ~sep:"@ " pp_vhdl_package)
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    d.packages
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    (fun fmt -> if d.packages <> [] then Format.fprintf fmt "@ ")
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    (Utils.fprintf_list ~sep:"@ " pp_vhdl_load)
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    d.libraries
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    (fun fmt -> if d.libraries <> [] then Format.fprintf fmt "@ ")
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    (Utils.fprintf_list ~sep:"@ " pp_vhdl_entity)
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    d.entities
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    (fun fmt -> if d.entities <> [] then Format.fprintf fmt "@ ")
482 ca7ff3f7 Lélio Brun
    (Utils.fprintf_list ~sep:"@ " pp_vhdl_architecture)
483
    d.architectures
484 91cc0f70 ploc
    (fun fmt -> if d.architectures <> [] then Format.fprintf fmt "@ ")