Project

General

Profile

« Previous | Next » 

Revision b0c77300

Added by Arnaud Dieumegard over 3 years ago

PP update: component instantiation type, archi format, port & generic decl in components, signal conditions, return statements expression

View differences:

src/backends/VHDL/vhdl_ast.ml
181 181
  | ProcedureCall of { label: vhdl_name_t [@default NoName]; name: vhdl_name_t; assocs: vhdl_assoc_element_t list [@default []] } [@name "PROCEDURE_CALL_STATEMENT"]
182 182
  | Wait [@name "WAIT_STATEMENT"]
183 183
  | Null of { label: vhdl_name_t [@default NoName]} [@name "NULL_STATEMENT"]
184
  | Return of { label: vhdl_name_t [@default NoName]} [@name "RETURN_STATEMENT"]
184
  | Return of { label: vhdl_name_t option [@default None]; expr: vhdl_expr_t option [@default None]} [@name "RETURN_STATEMENT"]
185 185
and vhdl_if_case_t = 
186 186
  {
187 187
    if_cond: vhdl_expr_t;
......
300 300
  {
301 301
    name: vhdl_name_t;
302 302
    inst_unit: vhdl_name_t;
303
    inst_unit_type : string [@default ""];
303 304
    archi_name: vhdl_name_t option [@default None];
304 305
    generic_map: vhdl_assoc_element_t list [@default []];
305 306
    port_map: vhdl_assoc_element_t list [@default []];

Also available in: Unified diff