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open Vhdl_ast
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open Vhdl_ast_eq
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type mini_vhdl_component_instantiation_t =
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  {
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    name: vhdl_name_t;
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    archi: vhdl_architecture_t;
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    entity: vhdl_entity_t;
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    generic_map: vhdl_assoc_element_t list [@default []];
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    port_map: vhdl_assoc_element_t list [@default []];
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  }
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[@@deriving show { with_path = false }];;
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type mini_vhdl_concurrent_stmt_t =
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  | SigAssign of vhdl_conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
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  | Process of vhdl_process_t [@name "PROCESS_STATEMENT"]
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  | SelectedSig of vhdl_selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
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  | ComponentInst of mini_vhdl_component_instantiation_t [@name "COMPONENT_INSTANTIATION_STATEMENT"]
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[@@deriving show { with_path = false }];;
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type mini_vhdl_component_t =
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  {
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    names: vhdl_name_t list [@default NoName];
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    generics: vhdl_port_t list [@default []]; (* From related 'entity' *)
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    ports: vhdl_port_t list [@default []]; (* From related 'entity' *)
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    contexts: vhdl_load_t list [@default []]; (* Related 'declarations' contexts + relatated entity contexts *)
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    declarations: vhdl_declaration_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
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    definitions: vhdl_definition_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
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    body: mini_vhdl_concurrent_stmt_t list [@key "ARCHITECTURE_STATEMENT_PART"] [@default []]; (* + entity.stmts *)
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  }
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[@@deriving show { with_path = false }];;
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type mini_vhdl_design_file_t = 
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  {
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    components: mini_vhdl_component_t list [@default []];
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    packages: vhdl_package_t list [@default []];
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  }
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[@@deriving show { with_path = false }];;
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