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Revision 92aface4

Added by Arnaud Dieumegard over 3 years ago

Removed warnings and solved bug for visitors iterators references between vhdl_ast and mini_vhdl_ast

View differences:

src/backends/VHDL/mini_vhdl_ast.ml
1 1
open Vhdl_ast
2 2

  
3 3
type mini_vhdl_sequential_stmt_t = 
4
  | VarAssign of {
4
  | MiniVarAssign of {
5 5
      label: vhdl_name_t option;
6 6
      lhs: vhdl_name_t;
7 7
      rhs: vhdl_expr_t }
8
  | SigSeqAssign of {
8
  | MiniSigSeqAssign of {
9 9
      label: vhdl_name_t option;
10 10
      lhs: vhdl_name_t;
11 11
      rhs: vhdl_waveform_element_t list}
12
  | SigCondAssign of {
12
  | MiniSigCondAssign of {
13 13
      label: vhdl_name_t option;
14 14
      lhs: vhdl_name_t;
15 15
      rhs: vhdl_signal_condition_t list;
16 16
      delay: vhdl_expr_t option}
17
  | SigSelectAssign of {
17
  | MiniSigSelectAssign of {
18 18
      label: vhdl_name_t option;
19 19
      lhs: vhdl_name_t;
20 20
      sel: vhdl_expr_t;
21 21
      branches: vhdl_signal_selection_t list;
22 22
      delay: vhdl_expr_t option}
23
  | If of {
23
  | MiniIf of {
24 24
      label: vhdl_name_t option;
25 25
      if_cases: mini_vhdl_if_case_t list;
26 26
      default: mini_vhdl_sequential_stmt_t list}
27
  | Case of {
27
  | MiniCase of {
28 28
      label: vhdl_name_t option;
29 29
      guard: vhdl_expr_t;
30 30
      branches: mini_vhdl_case_item_t list }
31
  | Exit of {
31
  | MiniExit of {
32 32
      label: vhdl_name_t option;
33 33
      loop_label: string option;
34 34
      condition: vhdl_expr_t option}
35
  | Assert of {
35
  | MiniAssert of {
36 36
      label: vhdl_name_t option;
37 37
      cond: vhdl_expr_t;
38 38
      report: vhdl_expr_t;
39 39
      severity: vhdl_expr_t}
40
  | ProcedureCall of {
40
  | MiniProcedureCall of {
41 41
      label: vhdl_name_t option;
42 42
      name: vhdl_name_t;
43 43
      assocs: vhdl_assoc_element_t list }
44
  | Wait
45
  | Null of {
44
  | MiniWait
45
  | MiniNull of {
46 46
      label: vhdl_name_t option}
47
  | Return of {
47
  | MiniReturn of {
48 48
     label: vhdl_name_t option;
49 49
     expr: vhdl_expr_t option}
50 50
and mini_vhdl_if_case_t =
......
59 59
  }
60 60

  
61 61
and mini_vhdl_declaration_t =
62
  | VarDecl of {
62
  | MiniVarDecl of {
63 63
      names : vhdl_name_t list;
64 64
      typ : vhdl_subtype_indication_t;
65 65
      init_val : vhdl_expr_t
66 66
    }
67
  | CstDecl of {
67
  | MiniCstDecl of {
68 68
      names : vhdl_name_t list;
69 69
      typ : vhdl_subtype_indication_t;
70 70
      init_val : vhdl_expr_t
71 71
    }
72
  | SigDecl of {
72
  | MiniSigDecl of {
73 73
      names : vhdl_name_t list;
74 74
      typ : vhdl_subtype_indication_t;
75 75
      init_val : vhdl_expr_t
76 76
    }
77
  | ComponentDecl of {
77
  | MiniComponentDecl of {
78 78
      name: vhdl_name_t;
79 79
      generics: vhdl_port_t list;
80 80
      ports: vhdl_port_t list;
81 81
    }
82
  | Subprogram of {
82
  | MiniSubprogram of {
83 83
      spec: vhdl_subprogram_spec_t;
84 84
      decl_part: mini_vhdl_declaration_t list;
85 85
      stmts: mini_vhdl_sequential_stmt_t list
......
112 112
  }
113 113

  
114 114
and mini_vhdl_concurrent_stmt_t =
115
  | Process of mini_vhdl_process_t
116
  | ComponentInst of mini_vhdl_component_instantiation_t
115
  | MiniProcess of mini_vhdl_process_t
116
  | MiniComponentInst of mini_vhdl_component_instantiation_t
117 117

  
118 118
and mini_vhdl_package_t =
119 119
  {
......
140 140
    packages: mini_vhdl_package_t list;
141 141
  }
142 142
(*[@@deriving show { with_path = false }]*)
143
[@@deriving visitors { variety = "iter"; name = "mini_vhdl_iter" }]
143
[@@deriving visitors { variety = "iter"; name = "mini_vhdl_iter"; ancestors = ["vhdl_iter"] }]
src/backends/VHDL/mini_vhdl_ast_pp.ml
75 75
  ((let open! Ppx_deriving_runtime in
76 76
      fun fmt  ->
77 77
        function
78
        | VarAssign { label = alabel; lhs = alhs; rhs = arhs } ->
78
        | MiniVarAssign { label = alabel; lhs = alhs; rhs = arhs } ->
79 79
            (match alabel with
80 80
              | None -> Format.fprintf fmt "";
81 81
              | Some e -> (((__0 ()) fmt) e;
......
84 84
            ((__1 ()) fmt) alhs;
85 85
            Format.fprintf fmt " := ";
86 86
            ((__2 ()) fmt) arhs;
87
        | SigSeqAssign { label = alabel; lhs = alhs; rhs = arhs } ->
87
        | MiniSigSeqAssign { label = alabel; lhs = alhs; rhs = arhs } ->
88 88
            (match alabel with
89 89
              | None -> Format.fprintf fmt "";
90 90
              | Some e -> (((__3 ()) fmt) e;
......
103 103
                        ((__5 ()) fmt) x;
104 104
                        true) false x);
105 105
            Format.fprintf fmt "@]@]")) arhs;
106
        | SigCondAssign { label = alabel; lhs = alhs; rhs = arhs; delay = adelay } ->
106
        | MiniSigCondAssign { label = alabel; lhs = alhs; rhs = arhs; delay = adelay } ->
107 107
            (match alabel with
108 108
              | None -> Format.fprintf fmt "";
109 109
              | Some e -> (((__6 ()) fmt) e;
......
126 126
                        ((__8 ()) fmt) x;
127 127
                        true) false x);
128 128
            Format.fprintf fmt "@]@]")) arhs;
129
        | SigSelectAssign
129
        | MiniSigSelectAssign
130 130
            { label = alabel; lhs = alhs; sel = asel; branches = abranches;
131 131
              delay = adelay }
132 132
            ->
......
154 154
                        ((__13 ()) fmt) x;
155 155
                        true) false x))) abranches;
156 156
            Format.fprintf fmt ";@]"
157
        | If { label = alabel; if_cases = aif_cases; default = adefault } ->
157
        | MiniIf { label = alabel; if_cases = aif_cases; default = adefault } ->
158 158
            (match alabel with
159 159
              | None -> Format.fprintf fmt "";
160 160
              | Some e -> (((__15 ()) fmt) e;
......
185 185
                          Format.fprintf fmt ";";
186 186
                          true) false x))) adefault));
187 187
            Format.fprintf fmt "@;end if@]"
188
        | Case { label = alabel; guard = aguard; branches = abranches } ->
188
        | MiniCase { label = alabel; guard = aguard; branches = abranches } ->
189 189
            (match alabel with
190 190
              | None -> Format.fprintf fmt "";
191 191
              | Some e -> (((__18 ()) fmt) e;
......
203 203
                          ((__20 ()) fmt) x;
204 204
                          true) false x);)) abranches;
205 205
            Format.fprintf fmt "@;end case@]";
206
        | Exit
206
        | MiniExit
207 207
            { label = alabel; loop_label = aloop_label;
208 208
              condition = acondition }
209 209
            ->
......
221 221
               | Some x ->
222 222
                   (Format.pp_print_string fmt "when@ ";
223 223
                    ((__22 ()) fmt) x;))) acondition;
224
        | Assert
224
        | MiniAssert
225 225
            { label = alabel; cond = acond; report = areport;
226 226
              severity = aseverity }
227 227
            ->
......
244 244
                Format.fprintf fmt "@;severity ";
245 245
                ((__26 ()) fmt) aseverity);
246 246
            Format.fprintf fmt "@]";
247
        | ProcedureCall { label = alabel; name = aname; assocs = aassocs } ->
247
        | MiniProcedureCall { label = alabel; name = aname; assocs = aassocs } ->
248 248
            (match alabel with
249 249
              | None -> Format.fprintf fmt "";
250 250
              | Some e -> (((__27 ()) fmt) e;
......
264 264
                          ((__29 ()) fmt) x;
265 265
                          true) false x))) aassocs;
266 266
               Format.fprintf fmt "@])");
267
        | Wait  -> Format.pp_print_string fmt "wait"
268
        | Null { label = alabel } ->
267
        | MiniWait  -> Format.pp_print_string fmt "wait"
268
        | MiniNull { label = alabel } ->
269 269
            (match alabel with
270 270
              | None -> Format.fprintf fmt "";
271 271
              | Some e -> (((__27 ()) fmt) e;
272 272
                     Format.fprintf fmt ":@ ")
273 273
            );
274 274
            Format.fprintf fmt "null";
275
        | Return { label = alabel; expr = aexpr } ->
275
        | MiniReturn { label = alabel; expr = aexpr } ->
276 276
            (match alabel with
277 277
              | None -> ();
278 278
              | Some a -> (((__28 ()) fmt) a;
......
387 387
  ((let open! Ppx_deriving_runtime in
388 388
      fun fmt  ->
389 389
        function
390
        | VarDecl { names = anames; typ = atyp; init_val = ainit_val } ->
390
        | MiniVarDecl { names = anames; typ = atyp; init_val = ainit_val } ->
391 391
            (Format.fprintf fmt "variable ";
392 392
             ((((fun x  ->
393 393
                    ignore
......
404 404
                | _ ->
405 405
                    (Format.fprintf fmt ":=";
406 406
                     ((__2 ()) fmt) ainit_val;))));)
407
        | CstDecl { names = anames; typ = atyp; init_val = ainit_val } ->
407
        | MiniCstDecl { names = anames; typ = atyp; init_val = ainit_val } ->
408 408
            (Format.fprintf fmt "constant ";
409 409
             ((((fun x  ->
410 410
                    ignore
......
418 418
              ((__4 ()) fmt) atyp;
419 419
              Format.fprintf fmt " := ";
420 420
              ((__5 ()) fmt) ainit_val)))
421
        | SigDecl { names = anames; typ = atyp; init_val = ainit_val } ->
421
        | MiniSigDecl { names = anames; typ = atyp; init_val = ainit_val } ->
422 422
            (Format.fprintf fmt "signal ";
423 423
            ((fun x  ->
424 424
              ignore
......
436 436
              | _ ->
437 437
                  (Format.fprintf fmt ":=";
438 438
                  ((__8 ()) fmt) ainit_val;)))
439
        | ComponentDecl
439
        | MiniComponentDecl
440 440
            { name = aname; generics = agenerics; ports = aports } ->
441 441
            Format.fprintf fmt "@[<v 2>component ";
442 442
            ((__9 ()) fmt) aname;
......
468 468
                            true) false x))) aports;
469 469
                Format.fprintf fmt "@]);");
470 470
            Format.fprintf fmt "@]@;end component";
471
        | Subprogram
471
        | MiniSubprogram
472 472
            { spec = aspec; decl_part = adecl_part; stmts = astmts }
473 473
            ->
474 474
              Format.fprintf fmt "@[<v 2>";
......
663 663
  ((let open! Ppx_deriving_runtime in
664 664
      fun fmt  ->
665 665
        function
666
        | Process a0 ->
666
        | MiniProcess a0 ->
667 667
             ((__0 ()) fmt) a0;
668
        | ComponentInst a0 ->
668
        | MiniComponentInst a0 ->
669 669
             ((__1 ()) fmt) a0;
670 670
    )
671 671
    [@ocaml.warning "-A"])
src/backends/VHDL/mini_vhdl_utils.ml
3 3

  
4 4
let mini_vhdl_declaration_t_names decl=
5 5
  match decl with
6
  | SigDecl { names; typ; init_val } -> names
6
  | MiniSigDecl { names; typ; init_val } -> names
7 7
  | _ -> []
8 8

  
9 9
let rec remove_opt l=
src/backends/VHDL/vhdl_2_mini_vhdl_map.ml
286 286
    method mini_vhdl_concurrent_stmt_t_assigned_signals_names : mini_vhdl_concurrent_stmt_t -> vhdl_name_t list=
287 287
      fun x ->
288 288
        match x with
289
        | Process a -> List.sort_uniq compare (
289
        | MiniProcess a -> List.sort_uniq compare (
290 290
            List.flatten (List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names a.p_body)
291 291
          )
292
        | ComponentInst a ->
292
        | MiniComponentInst a ->
293 293
            let out_ports_positions = get_ports_pos a.entity.ports OutPort 0 in
294 294
            let inout_ports_positions = get_ports_pos a.entity.ports InoutPort 0 in
295 295
            let assigned_out_ports_names = List.map (fun x -> x.actual_designator) a.port_map in
......
300 300
      mini_vhdl_sequential_stmt_t -> vhdl_name_t list=
301 301
      fun x  ->
302 302
        match x with
303
        | VarAssign { label; lhs; rhs } -> []
304
        | SigSeqAssign { label; lhs; rhs } -> [lhs]
305
        | SigCondAssign { label; lhs; rhs; delay} -> [lhs]
306
        | SigSelectAssign { label; lhs; sel; branches; delay } -> [lhs]
307
        | If { label; if_cases; default } -> 
303
        | MiniVarAssign { label; lhs; rhs } -> []
304
        | MiniSigSeqAssign { label; lhs; rhs } -> [lhs]
305
        | MiniSigCondAssign { label; lhs; rhs; delay} -> [lhs]
306
        | MiniSigSelectAssign { label; lhs; sel; branches; delay } -> [lhs]
307
        | MiniIf { label; if_cases; default } -> 
308 308
            let if_cases_stmts = List.flatten (List.map (fun x -> x.if_block_mini) if_cases) in
309 309
            List.flatten (List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names (if_cases_stmts@default))
310
        | Case { label; guard; branches } ->
310
        | MiniCase { label; guard; branches } ->
311 311
            let case_branches_stmts = List.flatten (List.map (fun x -> x.when_stmt_mini) branches) in
312 312
            List.flatten (List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names case_branches_stmts)
313
        | ProcedureCall { label; name; assocs } -> [] (* TODO: resolve this *)
313
        | MiniProcedureCall { label; name; assocs } -> [] (* TODO: resolve this *)
314 314
        | _ -> []
315 315

  
316 316
(****************
......
324 324
    method mini_vhdl_concurrent_stmt_t_memories : vhdl_name_t list -> mini_vhdl_concurrent_stmt_t -> vhdl_name_t list=
325 325
      fun assigned_signals -> fun x ->
326 326
        match x with
327
        | Process a -> List.flatten (List.map (self#memories assigned_signals []) a.p_body)
328
        | ComponentInst a -> [] (* Nothing to be reported here as memories are checked for each component *)
327
        | MiniProcess a -> List.flatten (List.map (self#memories assigned_signals []) a.p_body)
328
        | MiniComponentInst a -> [] (* Nothing to be reported here as memories are checked for each component *)
329 329

  
330 330
    method memories: vhdl_name_t list -> vhdl_name_t list -> mini_vhdl_sequential_stmt_t -> vhdl_name_t list=
331 331
      fun assigned_signals -> fun mems -> fun x ->
332 332
        match x with
333
        | If { label; if_cases; default } ->
333
        | MiniIf { label; if_cases; default } ->
334 334
            let if_cases_stmts = List.map (fun x -> x.if_block_mini) if_cases in
335 335
            let if_cases_assigned_signals = 
336 336
              List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names (List.flatten (if_cases_stmts@[default])) in
......
339 339
            (match default with
340 340
              | [] -> (List.flatten if_cases_assigned_signals)@mems
341 341
              | _ -> mems)
342
        | Case { label; guard; branches } ->
342
        | MiniCase { label; guard; branches } ->
343 343
            let case_branches_stmts = List.map (fun x -> x.when_stmt_mini) branches in
344 344
         (*   let case_assigned_signals = List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names (List.flatten (case_branches_stmts)) in *)
345 345
            let cases_memories = List.flatten (List.map (fun x -> List.flatten (List.map (self#memories assigned_signals []) x)) (case_branches_stmts)) in
......
616 616
        | VarAssign { label; seqs_lhs; rhs } ->
617 617
            let label = self#option self#lower_vhdl_name_t label in
618 618
            let lhs = self#lower_vhdl_name_t seqs_lhs  in
619
            let rhs = self#vhdl_expr_t rhs  in VarAssign { label; lhs; rhs }
619
            let rhs = self#vhdl_expr_t rhs  in MiniVarAssign { label; lhs; rhs }
620 620
        | SigSeqAssign { label; seqs_lhs; rhs } ->
621 621
            let label = self#option self#lower_vhdl_name_t label in
622 622
            let lhs = self#lower_vhdl_name_t seqs_lhs  in
623 623
            let rhs = self#list self#vhdl_waveform_element_t rhs in
624
            SigSeqAssign { label; lhs; rhs }
624
            MiniSigSeqAssign { label; lhs; rhs }
625 625
        | If { label; if_cases; default } ->
626 626
            let label = self#option self#lower_vhdl_name_t label in
627 627
            let if_cases = List.map self#vhdl_if_case_t if_cases  in
628 628
            let default = List.map self#vhdl_sequential_stmt_t default  in
629
            If { label; if_cases; default }
629
            MiniIf { label; if_cases; default }
630 630
        | Case { label; guard; branches } ->
631 631
            let label = self#option self#lower_vhdl_name_t label in
632 632
            let guard = self#vhdl_expr_t guard  in
633 633
            let branches = List.map self#vhdl_case_item_t branches  in
634
            Case { label; guard; branches }
634
            MiniCase { label; guard; branches }
635 635
        | Exit { label; loop_label; condition } ->
636 636
            let label = self#option self#lower_vhdl_name_t label in
637 637
            let loop_label = self#option self#string loop_label  in
638 638
            let condition = self#option self#vhdl_expr_t condition  in
639
            Exit { label; loop_label; condition }
639
            MiniExit { label; loop_label; condition }
640 640
        | Assert { label; cond; report; severity } ->
641 641
            let label = self#option self#lower_vhdl_name_t label in
642 642
            let cond = self#vhdl_expr_t cond  in
643 643
            let report = self#vhdl_expr_t report  in
644 644
            let severity = self#vhdl_expr_t severity  in
645
            Assert { label; cond; report; severity }
645
            MiniAssert { label; cond; report; severity }
646 646
        | ProcedureCall { label; name; assocs } ->
647 647
            let label = self#option self#lower_vhdl_name_t label in
648 648
            let name = self#lower_vhdl_name_t name  in
649 649
            let assocs = self#list self#vhdl_assoc_element_t assocs  in
650 650
            (* TODO: get procedure declaration and map assoc_elements *)
651
            ProcedureCall { label; name; assocs }
652
        | Wait  -> Wait
651
            MiniProcedureCall { label; name; assocs }
652
        | Wait  -> MiniWait
653 653
        | Null { label } ->
654 654
            let label = self#option self#lower_vhdl_name_t label in
655
            Null { label }
655
            MiniNull { label }
656 656
        | Return { label; expr } ->
657 657
            let label = self#option self#lower_vhdl_name_t label  in
658 658
            let expr = self#option self#vhdl_expr_t expr in
659
            Return { label; expr }
659
            MiniReturn { label; expr }
660 660

  
661 661
    method vhdl_if_case_t : vhdl_if_case_t -> mini_vhdl_if_case_t=
662 662
      fun { if_cond; if_block }  ->
......
677 677
            let names = self#list self#lower_vhdl_name_t names  in
678 678
            let typ = self#vhdl_subtype_indication_t typ  in
679 679
            let init_val = self#vhdl_expr_t init_val  in
680
            VarDecl { names; typ; init_val }
680
            MiniVarDecl { names; typ; init_val }
681 681
        | CstDecl { names; typ; init_val } ->
682 682
            let names = self#list self#lower_vhdl_name_t names  in
683 683
            let typ = self#vhdl_subtype_indication_t typ  in
684 684
            let init_val = self#vhdl_expr_t init_val  in
685
            CstDecl { names; typ; init_val }
685
            MiniCstDecl { names; typ; init_val }
686 686
        | SigDecl { names; typ; init_val } ->
687 687
            let names = self#list self#lower_vhdl_name_t names  in
688 688
            let typ = self#vhdl_subtype_indication_t typ  in
689 689
            let init_val = self#vhdl_expr_t init_val  in
690
            SigDecl { names; typ; init_val }
690
            MiniSigDecl { names; typ; init_val }
691 691
        | ComponentDecl { name; generics; ports } ->
692 692
            let name = self#lower_vhdl_name_t name  in
693 693
            let generics = self#list self#vhdl_port_t generics  in
694 694
            let ports = self#list self#vhdl_port_t ports  in
695
            ComponentDecl { name; generics; ports }
695
            MiniComponentDecl { name; generics; ports }
696 696
        | Subprogram { spec; decl_part; stmts } ->
697 697
            let spec = self#vhdl_subprogram_spec_t spec  in
698 698
            let decl_part = List.map self#vhdl_declaration_t decl_part  in
699 699
            let stmts = List.map self#vhdl_sequential_stmt_t stmts  in
700 700
            (* TODO: Explicit memories *)
701
            Subprogram { spec; decl_part; stmts }
701
            MiniSubprogram { spec; decl_part; stmts }
702 702

  
703 703
    method vhdl_declarative_item_t :
704 704
      vhdl_declarative_item_t -> mini_vhdl_declarative_item_t=
......
792 792
      fun x  ->
793 793
        match x with
794 794
        | SigAssign a -> 
795
            Process {
795
            MiniProcess {
796 796
              id = self#postfix_flatten_vhdl_name_t a.cs_lhs "__implicit_process";
797 797
              p_declarations = [];
798 798
              active_sigs = get_sensitivity_list#vhdl_concurrent_stmt_t x [];
799
              p_body = (SigCondAssign {
799
              p_body = (MiniSigCondAssign {
800 800
                label = None;
801 801
                lhs = a.cs_lhs;
802 802
                rhs = a.rhs;
......
805 805
              postponed = a.cs_postponed;
806 806
              label = match a.cs_label with | NoName -> None | _ -> Some a.cs_label
807 807
            }
808
        | Process a -> let a = self#vhdl_process_t a  in Process a
808
        | Process a -> let a = self#vhdl_process_t a  in MiniProcess a
809 809
        | SelectedSig a -> 
810
            Process {
810
            MiniProcess {
811 811
              id = self#postfix_flatten_vhdl_name_t a.ss_lhs "__implicit_process";
812 812
              p_declarations = [];
813 813
              active_sigs = get_sensitivity_list#vhdl_concurrent_stmt_t x [];
814
              p_body = (SigSelectAssign {
814
              p_body = (MiniSigSelectAssign {
815 815
                label = None;
816 816
                lhs = a.ss_lhs;
817 817
                sel = a.sel;
......
821 821
              postponed = a.ss_postponed;
822 822
              label = match a.ss_label with | NoName -> None | _ -> Some a.ss_label
823 823
            }
824
        | ComponentInst a -> let a = self#vhdl_component_instantiation_t a  in ComponentInst a
824
        | ComponentInst a -> let a = self#vhdl_component_instantiation_t a  in MiniComponentInst a
825 825

  
826 826
    method vhdl_port_t : vhdl_port_t -> vhdl_port_t=
827 827
      fun { port_names; port_mode; port_typ; port_expr }  ->
......
875 875
          let rec find_decls c_declarations acc_s acc_p = 
876 876
            match c_declarations with
877 877
            | [] -> (acc_s, acc_p)
878
            | (SigDecl (s))::tl -> find_decls tl ((SigDecl (s))::acc_s) (acc_p)
879
            | (Subprogram (s))::tl -> find_decls tl (acc_s) ((Subprogram (s))::acc_p)
878
            | (MiniSigDecl (s))::tl -> find_decls tl ((MiniSigDecl (s))::acc_s) (acc_p)
879
            | (MiniSubprogram (s))::tl -> find_decls tl (acc_s) ((MiniSubprogram (s))::acc_p)
880 880
            | _::tl -> find_decls tl acc_s acc_p in find_decls c_declarations [] [] in
881 881
        let assigned_signals_names = List.flatten (List.map self#mini_vhdl_concurrent_stmt_t_assigned_signals_names c_body) in
882 882
        let functions = List.map (
883
          fun x -> match x with Subprogram (s) -> (Simple s.spec.ss_name, s.spec.parameters, s.spec.typeMark) | _ -> failwith "Unreachable error (map on subprograms)"
883
          fun x -> match x with MiniSubprogram (s) -> (Simple s.spec.ss_name, s.spec.parameters, s.spec.typeMark) | _ -> failwith "Unreachable error (map on subprograms)"
884 884
        ) subprograms in
885 885
        let memories = List.flatten (List.map (self#mini_vhdl_concurrent_stmt_t_memories assigned_signals_names) c_body) in
886 886
        let new_tuple = { entity=ref_ent; 
src/tools/importer/mini_vhdl_to_lustre.ml
334 334
      mini_vhdl_declaration_t -> var_decl list=
335 335
      fun x  ->
336 336
        match x with
337
        | VarDecl { names; typ; init_val } ->
337
        | MiniVarDecl { names; typ; init_val } ->
338 338
            self#lustre_mk_var_decl InPort names typ
339 339
(*            let names = self#list self#vhdl_name_t names  in
340 340
            let typ = self#vhdl_subtype_indication_t typ  in
341 341
            let init_val = self#vhdl_expr_t init_val  in
342 342
            VarDecl { names; typ; init_val }*)
343
        | CstDecl { names; typ; init_val } ->
343
        | MiniCstDecl { names; typ; init_val } ->
344 344
            self#lustre_mk_var_decl InPort names typ
345 345
(*            let names = self#list self#vhdl_name_t names  in
346 346
            let typ = self#vhdl_subtype_indication_t typ  in
347 347
            let init_val = self#vhdl_expr_t init_val  in
348 348
            CstDecl { names; typ; init_val }*)
349
        | SigDecl { names; typ; init_val } ->
349
        | MiniSigDecl { names; typ; init_val } ->
350 350
            self#lustre_mk_var_decl InPort names typ
351 351
(*            let names = self#list self#vhdl_name_t names  in
352 352
            let typ = self#vhdl_subtype_indication_t typ  in
353 353
            let init_val = self#vhdl_expr_t init_val  in
354 354
            SigDecl { names; typ; init_val }*)
355
        | ComponentDecl { name; generics; ports } ->
355
        | MiniComponentDecl { name; generics; ports } ->
356 356
            []
357 357
(*            let name = self#vhdl_name_t name  in
358 358
            let generics = self#list self#vhdl_port_t generics  in
359 359
            let ports = self#list self#vhdl_port_t ports  in
360 360
            ComponentDecl { name; generics; ports }*)
361
        | Subprogram { spec; decl_part; stmts } ->
361
        | MiniSubprogram { spec; decl_part; stmts } ->
362 362
            []
363 363
(*            let spec = self#vhdl_subprogram_spec_t spec  in
364 364
            let decl_part = self#list self#mini_vhdl_declaration_t decl_part
......
409 409
      mini_vhdl_concurrent_stmt_t -> statement=
410 410
      fun x  ->
411 411
        match x with
412
        | Process a -> (*let a = self#mini_vhdl_process_t a in*)
412
        | MiniProcess a -> (*let a = self#mini_vhdl_process_t a in*)
413 413
            Eq {eq_lhs=["Process"];
414 414
                eq_rhs={expr_tag=Utils.new_tag (); expr_desc=Expr_ident "toto";
415 415
                        expr_type={tdesc=Tconst "cst"; tid=0}; expr_clock={cdesc=Cvar;cscoped=false;cid=0};
416 416
                        expr_delay={ddesc=Dundef;did=0}; expr_annot=None; expr_loc=Location.dummy_loc};
417 417
                eq_loc=Location.dummy_loc}
418
        | ComponentInst a ->
418
        | MiniComponentInst a ->
419 419
            let a = self#mini_vhdl_component_instantiation_t a  in a
420 420

  
421 421
    method mini_vhdl_package_t : mini_vhdl_package_t -> top_decl_desc=

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