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Revision 9195145a

Added by Arnaud Dieumegard almost 5 years ago

First version of implicit memories explicitation

View differences:

src/backends/VHDL/vhdl_2_mini_vhdl_map.ml
12 12
    mutable architecture_generics: vhdl_port_t list;
13 13
    mutable assigned_signals_names: vhdl_name_t list;
14 14
    mutable functions: (vhdl_name_t * vhdl_parameter_t list * vhdl_name_t) list;
15
    mutable memories: vhdl_name_t list;
15 16
    mutable contexts: vhdl_load_t list;
16 17
  }
17 18

  
......
158 159
    method to_string_vhdl_name_t : vhdl_name_t -> string=
159 160
      fun x  ->
160 161
        match x with
161
        | Simple a -> "Si:"^a
162
        | Identifier a -> "Id:"^a
162
        | Simple a -> a
163
        | Identifier a -> a
163 164
        | Selected a -> String.concat "." (List.map self#to_string_vhdl_name_t a)
164 165
        | Index { id; exprs } -> self#to_string_vhdl_name_t id
165 166
        | Slice { id; range } -> self#to_string_vhdl_name_t id
......
264 265
 *)
265 266

  
266 267
(*****************
267
 * Begin names_t extraction
268
 * Begin names_t extraction (assigned signals)
268 269
 *)
269 270
    method mini_vhdl_concurrent_stmt_t_assigned_signals_names : mini_vhdl_concurrent_stmt_t -> vhdl_name_t list=
270 271
      fun x ->
......
288 289
            List.flatten (List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names case_branches_stmts)
289 290
        | ProcedureCall { label; name; assocs } -> [] (* TODO: resolve this *)
290 291
        | _ -> []
292

  
291 293
(****************
292 294
 *End names_t extraction
293 295
 *)
294 296

  
297
(*****************
298
 * Begin Implicit memories extraction
299
 *)
300

  
301
    method mini_vhdl_concurrent_stmt_t_memories : vhdl_name_t list -> mini_vhdl_concurrent_stmt_t -> vhdl_name_t list=
302
      fun assigned_signals -> fun x ->
303
        match x with
304
        | Process a -> List.flatten (List.map (self#memories assigned_signals []) a.body)
305
        | ComponentInst a -> []
306

  
307
    method memories: vhdl_name_t list -> vhdl_name_t list -> mini_vhdl_sequential_stmt_t -> vhdl_name_t list=
308
      fun assigned_signals -> fun mems -> fun x ->
309
        match x with
310
        | If { label; if_cases; default } ->
311
            let if_cases_stmts = List.map (fun x -> x.if_block) if_cases in
312
            let if_cases_assigned_signals = 
313
              List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names (List.flatten (if_cases_stmts@[default])) in
314
            let if_cases_memories = List.flatten (List.map (fun x -> List.flatten (List.map (self#memories assigned_signals []) x)) (if_cases_stmts@[default])) in
315
            let mems = if_cases_memories@mems in
316

  
317
            (match default with
318
              | [] -> (List.flatten if_cases_assigned_signals)@mems
319
              | _ -> mems)
320
        | Case { label; guard; branches } ->
321
            let case_branches_stmts = List.map (fun x -> x.when_stmt) branches in
322
            let case_assigned_signals = List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names (List.flatten (case_branches_stmts)) in
323
            let cases_memories = List.flatten (List.map (fun x -> List.flatten (List.map (self#memories assigned_signals []) x)) (case_branches_stmts)) in
324
            cases_memories@mems
325
        | _ -> mems
326

  
327
(****************
328
 *End memories extraction
329
 *)
330

  
331

  
295 332
    method vhdl_cst_val_t : vhdl_cst_val_t -> vhdl_cst_val_t=
296 333
      fun x  ->
297 334
        match x with
......
588 625
            let spec = self#vhdl_subprogram_spec_t spec  in
589 626
            let decl_part = List.map self#vhdl_declaration_t decl_part  in
590 627
            let stmts = List.map self#vhdl_sequential_stmt_t stmts  in
628
            (* TODO: Explicit memories *)
591 629
            Subprogram { spec; decl_part; stmts }
592 630

  
593 631
    method vhdl_declarative_item_t :
......
636 674
        let declarations = List.map self#vhdl_declarative_item_t declarations  in
637 675
        let active_sigs = self#list self#lower_vhdl_name_t active_sigs  in
638 676
        let body = List.map self#vhdl_sequential_stmt_t body  in
677
        (* TODO: Explicit memories *)
639 678
        let postponed = false in
640 679
        let label = None in
641 680
        { id; declarations; active_sigs; body; postponed; label }
......
827 866
        let functions = List.map (
828 867
          fun x -> match x with Subprogram (s) -> (Simple s.spec.name, s.spec.parameters, s.spec.typeMark) | _ -> failwith "Unreachable error"
829 868
        ) subprograms in
830
        (* TODO: Flatten component instantiation from here *)
869
        let memories = List.flatten (List.map (self#mini_vhdl_concurrent_stmt_t_memories assigned_signals_names) body) in
831 870
        self#db_add_tuple { entity=ref_ent; 
832 871
                            architecture=arch; 
833 872
                            architecture_signals=signals;
......
835 874
                            architecture_generics=generics;
836 875
                            assigned_signals_names=assigned_signals_names;
837 876
                            functions=functions;
877
                            memories=memories;
838 878
                            contexts=contexts;
839 879
                          };
840 880
        { names; 

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