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open Vhdl_ast
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type mini_vhdl_component_t =
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{
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names: vhdl_name_t list [@default NoName];
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generics: vhdl_port_t list [@default []]; (* From related 'entity' *)
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ports: vhdl_port_t list [@default []]; (* From related 'entity' *)
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contexts: vhdl_load_t list [@default []]; (* Related 'declarations' contexts + relatated entity contexts *)
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declarations: vhdl_declaration_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
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definitions: vhdl_definition_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
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body: vhdl_concurrent_stmt_t list [@key "ARCHITECTURE_STATEMENT_PART"] [@default []]; (* + entity.stmts *)
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}
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[@@deriving show { with_path = false }, yojson {strict = false}];;
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type mini_vhdl_design_file_t =
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{
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components: mini_vhdl_component_t list [@default []];
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packages: vhdl_package_t list [@default []];
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}
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[@@deriving show { with_path = false }, yojson];;
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