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open Vhdl_ast
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open Vhdl_ast_pp
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open Mini_vhdl_ast
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open Vhdl_2_mini_vhdl_map
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open Lustre_types
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open Utils
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let _ = fun (_ : mini_vhdl_component_instantiation_t) -> ()
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let _ = fun (_ : mini_vhdl_concurrent_stmt_t) -> ()
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let _ = fun (_ : mini_vhdl_component_t) -> ()
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let _ = fun (_ : mini_vhdl_design_file_t) -> ()
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class virtual mini_vhdl_to_lustre_map =
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object (self)
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inherit vhdl_2_mini_vhdl_map
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method virtual list : 'a . ('a -> 'a) -> 'a list -> 'a list
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method virtual mini_vhdl_component_instantiation_t :
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mini_vhdl_component_instantiation_t -> statement
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method virtual mini_vhdl_concurrent_stmt_t :
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mini_vhdl_concurrent_stmt_t -> statement
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method virtual mini_vhdl_component_t :
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mini_vhdl_component_t -> top_decl_desc
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method virtual mini_vhdl_design_file_t :
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mini_vhdl_design_file_t -> program
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method mini_vhdl_component_instantiation_t :
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mini_vhdl_component_instantiation_t -> statement=
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fun { name; archi; entity; generic_map; port_map } ->
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let name = self#vhdl_name_t name in
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let archi = archi in
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let entity = entity in
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let generic_map = self#list self#vhdl_assoc_element_t generic_map in
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let port_map = self#list self#vhdl_assoc_element_t port_map in
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Eq {eq_lhs=[show_vhdl_name_t name];
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eq_rhs={expr_tag=Utils.new_tag (); expr_desc=Expr_ident "toto";
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expr_type={tdesc=Tconst "cst"; tid=0}; expr_clock={cdesc=Cvar;cscoped=false;cid=0};
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expr_delay={ddesc=Dundef;did=0}; expr_annot=None; expr_loc=Location.dummy_loc};
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eq_loc=Location.dummy_loc}
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method mini_vhdl_concurrent_stmt_t :
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mini_vhdl_concurrent_stmt_t -> statement=
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fun x ->
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match x with
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| SigAssign a ->
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let a = self#vhdl_conditional_signal_t a in
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Eq {eq_lhs=["SigAssign"];
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eq_rhs={expr_tag=Utils.new_tag (); expr_desc=Expr_ident "toto";
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expr_type={tdesc=Tconst "cst"; tid=0}; expr_clock={cdesc=Cvar;cscoped=false;cid=0};
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expr_delay={ddesc=Dundef;did=0}; expr_annot=None; expr_loc=Location.dummy_loc};
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eq_loc=Location.dummy_loc}
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| Process a -> let a = self#vhdl_process_t a in
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Eq {eq_lhs=["Process"];
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eq_rhs={expr_tag=Utils.new_tag (); expr_desc=Expr_ident "toto";
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expr_type={tdesc=Tconst "cst"; tid=0}; expr_clock={cdesc=Cvar;cscoped=false;cid=0};
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expr_delay={ddesc=Dundef;did=0}; expr_annot=None; expr_loc=Location.dummy_loc};
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eq_loc=Location.dummy_loc}
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| SelectedSig a ->
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let a = self#vhdl_selected_signal_t a in
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Eq {eq_lhs=["SelectedSig"];
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eq_rhs={expr_tag=Utils.new_tag (); expr_desc=Expr_ident "toto";
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expr_type={tdesc=Tconst "cst"; tid=0}; expr_clock={cdesc=Cvar;cscoped=false;cid=0};
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expr_delay={ddesc=Dundef;did=0}; expr_annot=None; expr_loc=Location.dummy_loc};
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eq_loc=Location.dummy_loc}
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| ComponentInst a ->
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let a = self#mini_vhdl_component_instantiation_t a in a
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method mini_vhdl_package_t : vhdl_package_t -> top_decl_desc=
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fun { name; shared_defs; shared_decls; shared_uses } ->
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let name = self#vhdl_name_t name in
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let shared_defs = self#list self#vhdl_definition_t shared_defs in
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let shared_decls = self#list self#vhdl_declaration_t shared_decls in
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let shared_uses = self#list self#vhdl_load_t shared_uses in
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let node_id = show_vhdl_name_t name in
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let node_type = Types.new_var () in
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let node_clock = Clocks.new_ck Cvar false in
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Node { node_id; node_type; node_clock;
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node_inputs=[]; node_outputs = []; node_locals = [];
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node_gencalls = []; node_checks = []; node_asserts = [];
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node_stmts = []; node_dec_stateless = false; node_stateless = None;
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node_spec = None; node_annot = [] }
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method mini_vhdl_component_t :
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mini_vhdl_component_t -> top_decl_desc=
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fun
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{ names; generics; ports; contexts; declarations; definitions; body }
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->
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let names = self#list self#vhdl_name_t names in
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let generics = self#list self#vhdl_port_t generics in
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let ports = self#list self#vhdl_port_t ports in
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let contexts = self#list self#vhdl_load_t contexts in
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let declarations = self#list self#vhdl_declaration_t declarations in
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let definitions = self#list self#vhdl_definition_t definitions in
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let body = List.map self#mini_vhdl_concurrent_stmt_t body in
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let node_id = String.concat "__" (List.map show_vhdl_name_t names) in
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let node_type = Types.new_var () in
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let node_clock = Clocks.new_ck Cvar false in
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Node { node_id; node_type; node_clock;
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node_inputs=[]; node_outputs = []; node_locals = [];
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node_gencalls = []; node_checks = []; node_asserts = [];
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node_stmts = body; node_dec_stateless = false; node_stateless = None;
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node_spec = None; node_annot = [] }
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method mini_vhdl_design_file_t :
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mini_vhdl_design_file_t -> program =
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fun { components; packages } ->
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let components = List.map self#mini_vhdl_component_t components in
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let packages = List.map self#mini_vhdl_package_t packages in
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let desc x = { top_decl_desc = x; top_decl_owner = ""; top_decl_itf = false; top_decl_loc = Location.dummy_loc } in
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let desc1 = List.map desc components in
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let desc2 = List.map desc packages in
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desc1 @ desc2
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end
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