1
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2
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node integrator_reset ( Fx : real ; ResetLevel : bool ; x0 : real )
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3
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returns ( out : real ) ;
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4
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let
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out = x0 -> if ( ResetLevel ) then x0 else ( Fx * 1.000000 ) + pre ( out );
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tel
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7
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8
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node ANGL ( in_Out1_76 : real )
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returns ( _180_In1_238 : real ) ;
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var Abs_Out1_79 : real ;
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Relational_Operator_ANGL_Out1_101 : bool ;
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Sum6_Out1_111 : real ;
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Switch1_ANGL_Out1_120 : real ;
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-- sign_Out1_127 : real ;
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times360_Out1_226 : real ;
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Abs_In1_78 : real ;
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Relational_Operator_ANGL_In1_99 : real ;
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Sum6_In1_109 : real ;
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Sum6_In2_110 : real ;
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Switch1_ANGL_In1_117 : real ;
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Switch1_ANGL_In2_118 : bool ;
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Switch1_ANGL_In3_119 : real ;
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sign_In1_126 : real ;
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let
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Abs_Out1_79 = if Abs_In1_78 < 0.000000 then - Abs_In1_78 else Abs_In1_78;
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Relational_Operator_ANGL_Out1_101 = Relational_Operator_ANGL_In1_99 > 180.0;
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Sum6_Out1_111 = - Sum6_In1_109 + Sum6_In2_110;
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Switch1_ANGL_Out1_120 = if Switch1_ANGL_In2_118 then Switch1_ANGL_In1_117 else Switch1_ANGL_In3_119;
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-- sign_Out1_127 = ANGL_sign ( sign_In1_126 );
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-- times360_Out1_226 = 360.0 * sign_Out1_127;
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times360_Out1_226 = if (sign_In1_126 >= 0.0) then 360.0 else -360.0;
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Relational_Operator_ANGL_In1_99 = Abs_Out1_79;
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Abs_In1_78 = in_Out1_76;
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Switch1_ANGL_In3_119 = in_Out1_76;
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Sum6_In2_110 = in_Out1_76;
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sign_In1_126 = in_Out1_76;
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_180_In1_238 = Switch1_ANGL_Out1_120;
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Sum6_In1_109 = times360_Out1_226;
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Switch1_ANGL_In1_117 = Sum6_Out1_111;
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Switch1_ANGL_In2_118 = Relational_Operator_ANGL_Out1_101;
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tel
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45
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46
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node DynamicSaturation ( up_Out1_293 : real ; u_Out1_303 : real ; lo_Out1_313 : real )
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returns ( y1_In1_355 : real ) ;
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var low_lim : real ;
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let
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y1_In1_355 = if (low_lim <= up_Out1_293) then low_lim else up_Out1_293;
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low_lim = if (lo_Out1_313 >= u_Out1_303) then lo_Out1_313 else u_Out1_303;
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tel
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53
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node HgdCmdProcessor ( Vt_Out1_19 : real ; HdgCmdMCP_Out1_29 : real ; Heading_Out1_39 : real )
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returns ( HdgCmd_In1_947 : real ; HdgRteCmd_In1_959 : real ;
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Integrator1 : real ; DynamicSat : real ) ;
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var
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var2zetaOmega_Out1_59 : real ;
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ANGL_Out1_66 : real ;
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DynamicSaturation_Out1_283 : real ;
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Integrator1_Out1_380 : real ;
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Logical_Operator_Out1_385 : bool ;
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Sum2_Out1_489 : real ;
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Sum3_Out1_499 : real ;
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k_Out1_723 : real ;
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66
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k1_Out1_732 : real ;
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67
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omegaSq2_Out1_783 : real ;
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68
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omega_calc_Out1_790 : real ;
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rateLim_calc_Out1_875 : real ;
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times514dot8_Out1_890 : real ;
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Integrator1_1_Out1_598 : real ;
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Logical_Operator1_1_Out1_604 : bool ;
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Logical_Operator1_2_Out1_610 : bool ;
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Logical_Operator1_3_Out1_616 : bool ;
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Relational_Operator_Out1_622 : bool ;
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Relational_Operator1_Out1_628 : bool ;
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Relational_Operator2_Out1_634 : bool ;
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78
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Relational_Operator3_Out1_640 : bool ;
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Switch1_Out1_649 : real ;
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Switch2_Out1_658 : real ;
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Switch3_Out1_667 : real ;
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var2zetaOmega_In1_57 : real ;
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ANGL_In1_65 : real ;
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DynamicSaturation_In1_280 : real ;
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DynamicSaturation_In2_281 : real ;
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DynamicSaturation_In3_282 : real ;
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Integrator1_In1_377 : real ;
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Integrator1_In2_378 : bool ;
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Integrator1_In3_379 : real ;
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Logical_Operator_In1_384 : bool ;
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Sum2_In1_487 : real ;
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Sum2_In2_488 : real ;
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Sum3_In1_497 : real ;
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Sum3_In2_498 : real ;
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k_In1_722 : real ;
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k1_In1_731 : real ;
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omegaSq2_In2_782 : real ;
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Integrator1_1_In1_595 : real ;
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Integrator1_1_In2_596 : bool ;
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-- Integrator1_1_In3_597 : real ;
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Logical_Operator1_1_In1_602 : bool ;
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Logical_Operator1_1_In2_603 : bool ;
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Logical_Operator1_2_In1_608 : bool ;
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Logical_Operator1_2_In2_609 : bool ;
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Logical_Operator1_3_In1_614 : bool ;
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Logical_Operator1_3_In2_615 : bool ;
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Relational_Operator_In1_620 : real ;
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Relational_Operator_In2_621 : real ;
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Relational_Operator1_In1_626 : real ;
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Relational_Operator1_In2_627 : real ;
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111
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Relational_Operator2_In1_632 : real ;
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112
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-- Relational_Operator2_In2_633 : real ;
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Relational_Operator3_In1_638 : real ;
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114
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-- Relational_Operator3_In2_639 : real ;
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115
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Switch1_In1_646 : real ;
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Switch1_In2_647 : bool ;
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117
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Switch1_In3_648 : real ;
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Switch2_In1_655 : real ;
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Switch2_In2_656 : bool ;
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Switch2_In3_657 : real ;
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Switch3_In2_665 : bool ;
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Switch3_In3_666 : real ;
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123
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124
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let
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125
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var2zetaOmega_Out1_59 = var2zetaOmega_In1_57 * -3.2;
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126
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127
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-- I 'sliced' the model (we would need to add simpler versions
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128
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-- for the other cases to be complete)
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-- ANGL_Out1_66 = ANGL ( ANGL_In1_65 );
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ANGL_Out1_66 = ANGL_In1_65;
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131
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132
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DynamicSaturation_Out1_283 = DynamicSaturation ( DynamicSaturation_In1_280 , DynamicSaturation_In2_281 , DynamicSaturation_In3_282 );
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133
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134
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DynamicSat = ANGL_Out1_66;
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135
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Integrator1_Out1_380 = integrator_reset( Integrator1_In1_377 , Integrator1_In2_378 , Integrator1_In3_379);
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Logical_Operator_Out1_385 = not Logical_Operator_In1_384;
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138
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139
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Sum2_Out1_489 = Sum2_In1_487 + - Sum2_In2_488;
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Sum3_Out1_499 = Sum3_In1_497 + - Sum3_In2_498;
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141
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142
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k_Out1_723 = - 1.000000 * k_In1_722;
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143
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k1_Out1_732 = - 1.000000 * k1_In1_731;
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144
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omegaSq2_Out1_783 = 2.56 * omegaSq2_In2_782;
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145
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|
146
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omega_calc_Out1_790 = - 1.6;
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147
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|
148
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-- FALK: fix the constant between 90 and 600.
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149
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-- this is the output of ratelim.
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150
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rateLim_calc_Out1_875 = 300.0 * Vt_Out1_19;
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151
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|
152
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-- times block (548 / (Vt * 1.6))
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153
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times514dot8_Out1_890 = 305.0 * Vt_Out1_19 ;
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154
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|
155
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156
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Integrator1_1_Out1_598 = integrator_reset ( Integrator1_1_In1_595 , Integrator1_1_In2_596 , 0.000000);
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Logical_Operator1_1_Out1_604 = Logical_Operator1_1_In1_602 and Logical_Operator1_1_In2_603;
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158
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Logical_Operator1_2_Out1_610 = Logical_Operator1_2_In1_608 and Logical_Operator1_2_In2_609;
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159
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Logical_Operator1_3_Out1_616 = Logical_Operator1_3_In1_614 or Logical_Operator1_3_In2_615;
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160
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Relational_Operator_Out1_622 = Relational_Operator_In1_620 <= Relational_Operator_In2_621;
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161
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Relational_Operator1_Out1_628 = Relational_Operator1_In1_626 >= Relational_Operator1_In2_627;
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162
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Relational_Operator2_Out1_634 = Relational_Operator2_In1_632 > 0.000000;
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163
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Relational_Operator3_Out1_640 = Relational_Operator3_In1_638 < 0.000000;
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164
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Switch1_Out1_649 = if Switch1_In2_647 then Switch1_In1_646 else Switch1_In3_648;
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165
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Switch2_Out1_658 = if Switch2_In2_656 then Switch2_In1_655 else Switch2_In3_657;
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166
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Switch3_Out1_667 = if Switch3_In2_665 then 0.000000 else Switch3_In3_666;
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167
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|
168
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Sum2_In2_488 = Integrator1_Out1_380;
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169
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HdgCmd_In1_947 = Integrator1_Out1_380;
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170
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DynamicSaturation_In3_282 = k_Out1_723;
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171
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DynamicSaturation_In2_281 = Sum3_Out1_499;
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172
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k1_In1_731 = rateLim_calc_Out1_875;
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173
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var2zetaOmega_In1_57 = Switch2_Out1_658;
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174
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HdgRteCmd_In1_959 = Switch2_Out1_658;
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175
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Integrator1_In1_377 = Switch2_Out1_658;
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176
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Sum3_In2_498 = var2zetaOmega_Out1_59;
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177
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DynamicSaturation_In1_280 = times514dot8_Out1_890;
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178
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k_In1_722 = times514dot8_Out1_890;
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179
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Sum3_In1_497 = omegaSq2_Out1_783;
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180
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ANGL_In1_65 = Sum2_Out1_489;
|
181
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Logical_Operator_In1_384 = if HdgCmdMCP_Out1_29 = 0.000000 then false else true;
|
182
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Sum2_In1_487 = HdgCmdMCP_Out1_29;
|
183
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omegaSq2_In2_782 = ANGL_Out1_66;
|
184
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Integrator1_In2_378 = Logical_Operator_Out1_385;
|
185
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Integrator1_In3_379 = Heading_Out1_39;
|
186
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Relational_Operator1_In1_626 = k1_Out1_732;
|
187
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Switch2_In1_655 = k1_Out1_732;
|
188
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Integrator1_1_In2_596 = Logical_Operator_Out1_385;
|
189
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Switch3_In3_666 = DynamicSaturation_Out1_283;
|
190
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Relational_Operator3_In1_638 = DynamicSaturation_Out1_283;
|
191
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Relational_Operator2_In1_632 = DynamicSaturation_Out1_283;
|
192
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Relational_Operator_In1_620 = rateLim_calc_Out1_875;
|
193
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Switch1_In1_646 = rateLim_calc_Out1_875;
|
194
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Logical_Operator1_2_In2_609 = Relational_Operator1_Out1_628;
|
195
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Switch2_In2_656 = Relational_Operator1_Out1_628;
|
196
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Switch2_In3_657 = Switch1_Out1_649;
|
197
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Relational_Operator1_In2_627 = Switch1_Out1_649;
|
198
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Logical_Operator1_2_In1_608 = Relational_Operator3_Out1_640;
|
199
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Logical_Operator1_3_In2_615 = Logical_Operator1_2_Out1_610;
|
200
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Logical_Operator1_3_In1_614 = Logical_Operator1_1_Out1_604;
|
201
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Switch3_In2_665 = Logical_Operator1_3_Out1_616;
|
202
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Logical_Operator1_1_In2_603 = Relational_Operator2_Out1_634;
|
203
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Integrator1_1_In1_595 = Switch3_Out1_667;
|
204
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Logical_Operator1_1_In1_602 = Relational_Operator_Out1_622;
|
205
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Switch1_In2_647 = Relational_Operator_Out1_622;
|
206
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Relational_Operator_In2_621 = Integrator1_1_Out1_598;
|
207
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Switch1_In3_648 = Integrator1_1_Out1_598;
|
208
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Integrator1 = Integrator1_1_Out1_598;
|
209
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tel
|
210
|
|
211
|
|
212
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node top ( Vt : real ; HdgCmdMCP : real ; Heading : real)
|
213
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returns (obs : bool);
|
214
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var HdgCmd : real ;
|
215
|
HdgRteCmd : real;
|
216
|
preCmd : real;
|
217
|
prePreCmd : real;
|
218
|
prePrePreCmd : real;
|
219
|
count : int;
|
220
|
integ : real;
|
221
|
preInteg : real;
|
222
|
dsat : real;
|
223
|
let
|
224
|
|
225
|
HdgCmd, HdgRteCmd, integ, dsat = HgdCmdProcessor ( Vt, HdgCmdMCP , Heading);
|
226
|
|
227
|
assert (Vt >= 0.005) and (Vt <= 0.01);
|
228
|
assert true -> Vt = pre(Vt);
|
229
|
|
230
|
assert (HdgCmdMCP > 10.0) and (HdgCmdMCP < 170.0);
|
231
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assert (Heading > 0.0) and (Heading < 180.0);
|
232
|
|
233
|
assert Heading = 20.0;
|
234
|
assert HdgCmdMCP = 30.0;
|
235
|
|
236
|
assert true -> (HdgCmdMCP = pre(HdgCmdMCP));
|
237
|
|
238
|
assert (HdgCmdMCP >= Heading + 10);
|
239
|
|
240
|
count = 0 -> 1 + pre(count);
|
241
|
|
242
|
preCmd = 0.0 -> pre(HdgCmd);
|
243
|
prePreCmd = 0.0 -> pre(preCmd);
|
244
|
prePrePreCmd = 0.0 -> pre(prePreCmd);
|
245
|
preInteg = 0.0 -> pre(integ);
|
246
|
|
247
|
-- TIMEOUT
|
248
|
-- obs = true -> (count < 5) or
|
249
|
-- (((not (HdgCmdMCP > prePrePreCmd and prePrePreCmd > prePreCmd )) or ((HdgRteCmd > pre(HdgRteCmd)) or (HdgRteCmd > 0.0)) )
|
250
|
-- and ((not (HdgCmdMCP < prePrePreCmd and prePrePreCmd < prePreCmd )) or ((HdgRteCmd < pre(HdgRteCmd)) or (HdgRteCmd < 0.0)) ));
|
251
|
|
252
|
-- TIMEOUT
|
253
|
-- obs = true -> (count < 5) or ((HdgCmdMCP - HdgCmd < 10.0) and (HdgCmdMCP - HdgCmd > -10.0));
|
254
|
|
255
|
-- TIMEOUT
|
256
|
-- obs = true -> (count < 5) or
|
257
|
-- (((not (HdgCmdMCP > prePrePreCmd and prePrePreCmd > prePreCmd )) or ((integ > pre(integ)) or (integ > 0.0)) ) and
|
258
|
-- ((not (HdgCmdMCP < prePrePreCmd and prePrePreCmd < prePreCmd )) or ((integ < pre(integ)) or (integ < 0.0)) ));
|
259
|
|
260
|
-- TIMEOUT
|
261
|
-- obs = ((not (HdgRteCmd < 1.0)) and (HdgRteCmd > -1.0)) and
|
262
|
-- ((HdgCmdMCP = Heading) or
|
263
|
-- ((HdgCmdMCP > Heading) and (HdgCmd > Heading)) or
|
264
|
-- ((HdgCmdMCP < Heading) and (HdgCmd < Heading)));
|
265
|
|
266
|
obs = true -> (count < 2) or
|
267
|
((HdgCmdMCP > preCmd) and (dsat > 0.0)) or
|
268
|
((HdgCmdMCP < preCmd) and (dsat < 0.01));
|
269
|
|
270
|
--!MAIN : true;
|
271
|
--!PROPERTY: obs = true;
|
272
|
tel
|