1
|
|
2
|
|
3
|
-- An integrator with reset
|
4
|
node integrator_reset ( Fx : real ; ResetLevel : bool ; x0 : real ) returns (o : real ) ;
|
5
|
let
|
6
|
o = x0 -> if ( ResetLevel ) then x0 else ( Fx * 1.000000 ) + pre ( o );
|
7
|
tel
|
8
|
|
9
|
node ANGL_sign ( SigIn_Out1_137 : real ) returns ( Out2_In1_203 : real ) ;
|
10
|
var Switch1_Out1_182 : real ;
|
11
|
let
|
12
|
Switch1_Out1_182 = if 0.000000 = SigIn_Out1_137 then 0.000000 else - 1.000000;
|
13
|
Out2_In1_203 = if SigIn_Out1_137 > 0.000000 then 1.000000 else Switch1_Out1_182;
|
14
|
tel
|
15
|
|
16
|
|
17
|
node ANGL ( in_Out1_76 : real ) returns ( _180_In1_238 : real ) ;
|
18
|
var Abs_Out1_79 : real ;
|
19
|
Relational_Operator_ANGL_Out1_101 : bool ;
|
20
|
Sum6_Out1_111 : real ;
|
21
|
Switch1_ANGL_Out1_120 : real ;
|
22
|
sign_Out1_127 : real ;
|
23
|
times360_Out1_226 : real ;
|
24
|
Abs_In1_78 : real ;
|
25
|
Relational_Operator_ANGL_In1_99 : real ;
|
26
|
Sum6_In1_109 : real ;
|
27
|
Sum6_In2_110 : real ;
|
28
|
Switch1_ANGL_In1_117 : real ;
|
29
|
Switch1_ANGL_In2_118 : bool ;
|
30
|
Switch1_ANGL_In3_119 : real ;
|
31
|
sign_In1_126 : real ;
|
32
|
|
33
|
let
|
34
|
Abs_Out1_79 = if Abs_In1_78 < 0.000000 then - Abs_In1_78 else Abs_In1_78;
|
35
|
Relational_Operator_ANGL_Out1_101 = Relational_Operator_ANGL_In1_99 > 180.000000;
|
36
|
Sum6_Out1_111 = - Sum6_In1_109 + Sum6_In2_110;
|
37
|
Switch1_ANGL_Out1_120 = if Switch1_ANGL_In2_118 then Switch1_ANGL_In1_117 else Switch1_ANGL_In3_119;
|
38
|
sign_Out1_127 = ANGL_sign ( sign_In1_126 );
|
39
|
times360_Out1_226 = 360.000000 * sign_Out1_127;
|
40
|
Relational_Operator_ANGL_In1_99 = Abs_Out1_79;
|
41
|
Abs_In1_78 = in_Out1_76;
|
42
|
Switch1_ANGL_In3_119 = in_Out1_76;
|
43
|
Sum6_In2_110 = in_Out1_76;
|
44
|
sign_In1_126 = in_Out1_76;
|
45
|
_180_In1_238 = Switch1_ANGL_Out1_120;
|
46
|
Sum6_In1_109 = times360_Out1_226;
|
47
|
Switch1_ANGL_In1_117 = Sum6_Out1_111;
|
48
|
Switch1_ANGL_In2_118 = Relational_Operator_ANGL_Out1_101;
|
49
|
tel
|
50
|
|
51
|
node DynamicSaturation ( up_Out1_293 : real ; u_Out1_303 : real ; lo_Out1_313 : real )
|
52
|
returns ( y1_In1_355 : real ) ;
|
53
|
var LowerRelop1_Out1_319 : bool ;
|
54
|
UpperRelop_Out1_325 : bool ;
|
55
|
switch2_1_Out1_334 : real ;
|
56
|
switch2_2_Out1_343 : real ;
|
57
|
LowerRelop1_In1_317 : real ;
|
58
|
LowerRelop1_In2_318 : real ;
|
59
|
UpperRelop_In1_323 : real ;
|
60
|
UpperRelop_In2_324 : real ;
|
61
|
switch2_1_In1_331 : real ;
|
62
|
switch2_1_In2_332 : bool ;
|
63
|
switch2_1_In3_333 : real ;
|
64
|
switch2_2_In1_340 : real ;
|
65
|
switch2_2_In2_341 : bool ;
|
66
|
switch2_2_In3_342 : real ;
|
67
|
|
68
|
let
|
69
|
LowerRelop1_Out1_319 = LowerRelop1_In1_317 > LowerRelop1_In2_318;
|
70
|
UpperRelop_Out1_325 = UpperRelop_In1_323 < UpperRelop_In2_324;
|
71
|
switch2_1_Out1_334 = if switch2_1_In2_332 then switch2_1_In1_331 else switch2_1_In3_333;
|
72
|
switch2_2_Out1_343 = if switch2_2_In2_341 then switch2_2_In1_340 else switch2_2_In3_342;
|
73
|
switch2_2_In1_340 = up_Out1_293;
|
74
|
LowerRelop1_In2_318 = up_Out1_293;
|
75
|
switch2_1_In3_333 = u_Out1_303;
|
76
|
LowerRelop1_In1_317 = u_Out1_303;
|
77
|
UpperRelop_In1_323 = u_Out1_303;
|
78
|
switch2_1_In1_331 = lo_Out1_313;
|
79
|
UpperRelop_In2_324 = lo_Out1_313;
|
80
|
switch2_2_In3_342 = switch2_1_Out1_334;
|
81
|
y1_In1_355 = switch2_2_Out1_343;
|
82
|
switch2_2_In2_341 = LowerRelop1_Out1_319;
|
83
|
switch2_1_In2_332 = UpperRelop_Out1_325;
|
84
|
tel
|
85
|
|
86
|
node Saturation ( signal : real ) returns ( saturated_signal : real ) ;
|
87
|
var low_lim : real ;
|
88
|
let
|
89
|
saturated_signal = if ( low_lim <= 1000.000000 ) then low_lim else 1000.000000;
|
90
|
low_lim = if ( 0.000100 >= signal ) then 0.000100 else signal;
|
91
|
tel
|
92
|
|
93
|
node HgdCmdProcessor ( Vt_Out1_19 : real ; HdgCmdMCP_Out1_29 : real ; Heading_Out1_39 : real )
|
94
|
returns ( HdgCmd_In1_947 : real ; HdgRteCmd_In1_959 : real ) ;
|
95
|
var var2zetaOmega_Out1_59 : real ;
|
96
|
ANGL_Out1_66 : real ;
|
97
|
Divide_Out1_262 : real ;
|
98
|
Divide1_Out1_274 : real ;
|
99
|
DynamicSaturation_Out1_283 : real ;
|
100
|
Integrator1_Out1_380 : real ;
|
101
|
Logical_Operator_Out1_385 : bool ;
|
102
|
Product_Out1_397 : real ;
|
103
|
Product1_Out1_409 : real ;
|
104
|
Saturation1_Out1_416 : real ;
|
105
|
Sum2_Out1_489 : real ;
|
106
|
Sum3_Out1_499 : real ;
|
107
|
Trigonometric_Function_Out1_504 : real ;
|
108
|
k_Out1_723 : real ;
|
109
|
k1_Out1_732 : real ;
|
110
|
k2_Out1_741 : real ;
|
111
|
k4_Out1_750 : real ;
|
112
|
k6_Out1_759 : real ;
|
113
|
omegaSq_Out1_771 : real ;
|
114
|
omegaSq2_Out1_783 : real ;
|
115
|
omega_calc_Out1_790 : real ;
|
116
|
rateLim_calc_Out1_875 : real ;
|
117
|
times514dot8_Out1_890 : real ;
|
118
|
Integrator1_1_Out1_598 : real ;
|
119
|
Logical_Operator1_1_Out1_604 : bool ;
|
120
|
Logical_Operator1_2_Out1_610 : bool ;
|
121
|
Logical_Operator1_3_Out1_616 : bool ;
|
122
|
Relational_Operator_Out1_622 : bool ;
|
123
|
Relational_Operator1_Out1_628 : bool ;
|
124
|
Relational_Operator2_Out1_634 : bool ;
|
125
|
Relational_Operator3_Out1_640 : bool ;
|
126
|
Switch1_Out1_649 : real ;
|
127
|
Switch2_Out1_658 : real ;
|
128
|
Switch3_Out1_667 : real ;
|
129
|
var2zetaOmega_In1_57 : real ;
|
130
|
var2zetaOmega_In2_58 : real ;
|
131
|
ANGL_In1_65 : real ;
|
132
|
DynamicSaturation_In1_280 : real ;
|
133
|
DynamicSaturation_In2_281 : real ;
|
134
|
DynamicSaturation_In3_282 : real ;
|
135
|
Integrator1_In1_377 : real ;
|
136
|
Integrator1_In2_378 : bool ;
|
137
|
Integrator1_In3_379 : real ;
|
138
|
Logical_Operator_In1_384 : bool ;
|
139
|
Product_In2_396 : real ;
|
140
|
Product1_In1_407 : real ;
|
141
|
Product1_In2_408 : real ;
|
142
|
Saturation1_In1_415 : real ;
|
143
|
Sum2_In1_487 : real ;
|
144
|
Sum2_In2_488 : real ;
|
145
|
Sum3_In1_497 : real ;
|
146
|
Sum3_In2_498 : real ;
|
147
|
Trigonometric_Function_In1_503 : real ;
|
148
|
k_In1_722 : real ;
|
149
|
k1_In1_731 : real ;
|
150
|
k2_In1_740 : real ;
|
151
|
k4_In1_749 : real ;
|
152
|
k6_In1_758 : real ;
|
153
|
omegaSq_In1_769 : real ;
|
154
|
omegaSq_In2_770 : real ;
|
155
|
omegaSq2_In1_781 : real ;
|
156
|
omegaSq2_In2_782 : real ;
|
157
|
omega_calc_In1_789 : real ;
|
158
|
rateLim_calc_In1_873 : real ;
|
159
|
rateLim_calc_In2_874 : real ;
|
160
|
times514dot8_In1_889 : real ;
|
161
|
Integrator1_1_In1_595 : real ;
|
162
|
Integrator1_1_In2_596 : bool ;
|
163
|
Logical_Operator1_1_In1_602 : bool ;
|
164
|
Logical_Operator1_1_In2_603 : bool ;
|
165
|
Logical_Operator1_2_In1_608 : bool ;
|
166
|
Logical_Operator1_2_In2_609 : bool ;
|
167
|
Logical_Operator1_3_In1_614 : bool ;
|
168
|
Logical_Operator1_3_In2_615 : bool ;
|
169
|
Relational_Operator_In1_620 : real ;
|
170
|
Relational_Operator_In2_621 : real ;
|
171
|
Relational_Operator1_In1_626 : real ;
|
172
|
Relational_Operator1_In2_627 : real ;
|
173
|
Relational_Operator2_In1_632 : real ;
|
174
|
Relational_Operator3_In1_638 : real ;
|
175
|
Switch1_In1_646 : real ;
|
176
|
Switch1_In2_647 : bool ;
|
177
|
Switch1_In3_648 : real ;
|
178
|
Switch2_In1_655 : real ;
|
179
|
Switch2_In2_656 : bool ;
|
180
|
Switch2_In3_657 : real ;
|
181
|
Switch3_In2_665 : bool ;
|
182
|
Switch3_In3_666 : real ;
|
183
|
integrator_out_1 : real ;
|
184
|
integrator_out_2 : real ;
|
185
|
let
|
186
|
assert true;
|
187
|
tel
|
188
|
|
189
|
node HeadingControl ( HdgCmdMCP_Out1_19 : real ; Heading_Out1_29 : real ; psidot_Out1_39 : real ; Vt_Out1_49 : real ; Roll_Out1_59 : real ; HeadEng_Out1_69 : bool ; rollLimitinput_Out1_79 : real )
|
190
|
returns ( RollCmd_In1_1442 : real ) ;
|
191
|
var HdgCmdProcessor_Out1_88 : real ;
|
192
|
HdgCmdProcessor_Out2_89 : real ;
|
193
|
Khdg_Out1_1105 : real ;
|
194
|
Khdg1_Out1_1114 : real ;
|
195
|
Khdg2_Out1_1123 : real ;
|
196
|
Khdgrte_Out1_1132 : real ;
|
197
|
Logical_Operator_Out1_1137 : bool ;
|
198
|
Max_Out1_1147 : real ;
|
199
|
Min_Out1_1157 : real ;
|
200
|
Mux_Out1_1161_0 : real ;
|
201
|
Mux_Out1_1161_1 : real ;
|
202
|
Sum_Out1_1171 : real ;
|
203
|
Sum1_Out1_1181 : real ;
|
204
|
Sum2_Out1_1191 : real ;
|
205
|
Sum3_Out1_1201 : real ;
|
206
|
Sum4_Out1_1211 : real ;
|
207
|
-- sgn_Out1_1430 : real ;
|
208
|
Integrator1_1_Out1_1305 : real ;
|
209
|
Logical_Operator1_1_Out1_1311 : bool ;
|
210
|
Logical_Operator1_2_Out1_1317 : bool ;
|
211
|
Logical_Operator1_3_Out1_1323 : bool ;
|
212
|
Relational_Operator_Out1_1329 : bool ;
|
213
|
Relational_Operator1_Out1_1335 : bool ;
|
214
|
Relational_Operator2_Out1_1341 : bool ;
|
215
|
Relational_Operator3_Out1_1347 : bool ;
|
216
|
Switch1_Out1_1356 : real ;
|
217
|
Switch2_Out1_1365 : real ;
|
218
|
Switch3_Out1_1374 : real ;
|
219
|
HdgCmdProcessor_In1_85 : real ;
|
220
|
HdgCmdProcessor_In2_86 : real ;
|
221
|
HdgCmdProcessor_In3_87 : real ;
|
222
|
Khdg_In1_1104 : real ;
|
223
|
Khdg1_In1_1113 : real ;
|
224
|
Khdg2_In1_1122 : real ;
|
225
|
Khdgrte_In1_1131 : real ;
|
226
|
Logical_Operator_In1_1136 : bool ;
|
227
|
Max_In1_1145 : real ;
|
228
|
Max_In2_1146 : real ;
|
229
|
Min_In1_1155 : real ;
|
230
|
Min_In2_1156 : real ;
|
231
|
Mux_In1_1159 : real ;
|
232
|
Mux_In2_1160 : real ;
|
233
|
Sum_In1_1169 : real ;
|
234
|
Sum_In2_1170 : real ;
|
235
|
Sum1_In1_1179 : real ;
|
236
|
Sum1_In2_1180 : real ;
|
237
|
Sum2_In1_1189 : real ;
|
238
|
Sum2_In2_1190 : real ;
|
239
|
Sum3_In1_1199 : real ;
|
240
|
Sum3_In2_1200 : real ;
|
241
|
Sum4_In1_1209 : real ;
|
242
|
Sum4_In2_1210 : real ;
|
243
|
-- sgn_In1_1429 : real ;
|
244
|
Integrator1_1_In1_1302 : real ;
|
245
|
Integrator1_1_In2_1303 : bool ;
|
246
|
Integrator1_1_In3_1304 : real ;
|
247
|
Logical_Operator1_1_In1_1309 : bool ;
|
248
|
Logical_Operator1_1_In2_1310 : bool ;
|
249
|
Logical_Operator1_2_In1_1315 : bool ;
|
250
|
Logical_Operator1_2_In2_1316 : bool ;
|
251
|
Logical_Operator1_3_In1_1321 : bool ;
|
252
|
Logical_Operator1_3_In2_1322 : bool ;
|
253
|
-- Relational_Operator_In1_1327 : real ;
|
254
|
Relational_Operator_In2_1328 : real ;
|
255
|
-- Relational_Operator1_In1_1333 : real ;
|
256
|
Relational_Operator1_In2_1334 : real ;
|
257
|
Relational_Operator2_In1_1339 : real ;
|
258
|
-- Relational_Operator2_In2_1340 : real ;
|
259
|
Relational_Operator3_In1_1345 : real ;
|
260
|
-- Relational_Operator3_In2_1346 : real ;
|
261
|
-- Switch1_In1_1353 : real ;
|
262
|
Switch1_In2_1354 : bool ;
|
263
|
Switch1_In3_1355 : real ;
|
264
|
-- Switch2_In1_1362 : real ;
|
265
|
Switch2_In2_1363 : bool ;
|
266
|
Switch2_In3_1364 : real ;
|
267
|
-- Switch3_In1_1371 : real ;
|
268
|
Switch3_In2_1372 : bool ;
|
269
|
Switch3_In3_1373 : real ;
|
270
|
integrator_out : real ;
|
271
|
let
|
272
|
HdgCmdProcessor_Out1_88 , HdgCmdProcessor_Out2_89 = HgdCmdProcessor ( HdgCmdProcessor_In1_85 , HdgCmdProcessor_In2_86 , HdgCmdProcessor_In3_87 );
|
273
|
Khdg_Out1_1105 = 0.050000 * Khdg_In1_1104;
|
274
|
-- Khdg1_Out1_1114 = int_to_real ( 1 ) *Khdg1_In1_1113;
|
275
|
Khdg1_Out1_1114 = Khdg1_In1_1113;
|
276
|
-- Khdg2_Out1_1123 = int_to_real ( 1 ) * Khdg2_In1_1122;
|
277
|
Khdg2_Out1_1123 = Khdg2_In1_1122;
|
278
|
Khdgrte_Out1_1132 = 3.0 * Khdgrte_In1_1131;
|
279
|
Logical_Operator_Out1_1137 = not Logical_Operator_In1_1136;
|
280
|
Max_Out1_1147 = if Max_In1_1145 >= Max_In2_1146 then Max_In2_1146 else Max_In1_1145;
|
281
|
Min_Out1_1157 = if Min_In1_1155 <= Min_In2_1156 then Min_In1_1155 else Min_In2_1156;
|
282
|
-- [ Mux_Out1_1161_0 , Mux_Out1_1161_1 ] = [ Mux_In1_1159 , Mux_In2_1160 ];
|
283
|
Mux_Out1_1161_0 = Mux_In1_1159 ;
|
284
|
Mux_Out1_1161_1 = Mux_In2_1160 ;
|
285
|
Sum_Out1_1171 = Sum_In1_1169 + - Sum_In2_1170;
|
286
|
Sum1_Out1_1181 = Sum1_In1_1179 + Sum1_In2_1180;
|
287
|
Sum2_Out1_1191 = Sum2_In1_1189 + - Sum2_In2_1190;
|
288
|
Sum3_Out1_1201 = - Sum3_In1_1199 + - Sum3_In2_1200;
|
289
|
Sum4_Out1_1211 = Sum4_In1_1209 + - Sum4_In2_1210;
|
290
|
-- sgn_Out1_1430 = int_to_real ( - 1 ) * sgn_In1_1429;
|
291
|
-- sgn_Out1_1430 = - 30.0;
|
292
|
integrator_out = integrator_reset ( Integrator1_1_In1_1302 , Integrator1_1_In2_1303 , Integrator1_1_In3_1304);
|
293
|
Integrator1_1_Out1_1305 = Integrator1_1_In3_1304 -> pre (integrator_out);
|
294
|
Logical_Operator1_1_Out1_1311 = Logical_Operator1_1_In1_1309 and Logical_Operator1_1_In2_1310;
|
295
|
Logical_Operator1_2_Out1_1317 = Logical_Operator1_2_In1_1315 and Logical_Operator1_2_In2_1316;
|
296
|
Logical_Operator1_3_Out1_1323 = Logical_Operator1_3_In1_1321 or Logical_Operator1_3_In2_1322;
|
297
|
-- Relational_Operator_Out1_1329 = Relational_Operator_In1_1327 <= Relational_Operator_In2_1328;
|
298
|
Relational_Operator_Out1_1329 = rollLimitinput_Out1_79 <= Relational_Operator_In2_1328;
|
299
|
-- Relational_Operator1_Out1_1335 = Relational_Operator1_In1_1333 >= Relational_Operator1_In2_1334;
|
300
|
Relational_Operator1_Out1_1335 = -rollLimitinput_Out1_79 >= Relational_Operator1_In2_1334;
|
301
|
-- Relational_Operator2_Out1_1341 = Relational_Operator2_In1_1339 > Relational_Operator2_In2_1340;
|
302
|
Relational_Operator2_Out1_1341 = Relational_Operator2_In1_1339 > 0.0;
|
303
|
-- Relational_Operator3_Out1_1347 = Relational_Operator3_In1_1345 < Relational_Operator3_In2_1346;
|
304
|
Relational_Operator3_Out1_1347 = Relational_Operator3_In1_1345 < 0.0;
|
305
|
-- Switch1_Out1_1356 = if Switch1_In2_1354 then Switch1_In1_1353 else Switch1_In3_1355;
|
306
|
Switch1_Out1_1356 = if Switch1_In2_1354 then rollLimitinput_Out1_79 else Switch1_In3_1355;
|
307
|
-- Switch2_Out1_1365 = if Switch2_In2_1363 then Switch2_In1_1362 else Switch2_In3_1364;
|
308
|
Switch2_Out1_1365 = if Switch2_In2_1363 then -rollLimitinput_Out1_79 else Switch2_In3_1364;
|
309
|
Switch3_Out1_1374 = if Switch3_In2_1372 then 0.0 else Switch3_In3_1373;
|
310
|
HdgCmdProcessor_In3_87 = Heading_Out1_29;
|
311
|
Sum_In2_1170 = Heading_Out1_29;
|
312
|
Sum_In1_1169 = HdgCmdProcessor_Out1_88;
|
313
|
Mux_In2_1160 = HdgCmdProcessor_Out1_88;
|
314
|
Khdg_In1_1104 = Sum_Out1_1171;
|
315
|
Sum1_In1_1179 = Khdg_Out1_1105;
|
316
|
Sum1_In2_1180 = Sum2_Out1_1191;
|
317
|
Sum2_In1_1189 = HdgCmdProcessor_Out2_89;
|
318
|
Sum2_In2_1190 = psidot_Out1_39;
|
319
|
HdgCmdProcessor_In1_85 = Vt_Out1_49;
|
320
|
HdgCmdProcessor_In2_86 = HdgCmdMCP_Out1_19;
|
321
|
Mux_In1_1159 = HdgCmdMCP_Out1_19;
|
322
|
RollCmd_In1_1442 = Switch2_Out1_1365;
|
323
|
Sum3_In1_1199 = Switch2_Out1_1365;
|
324
|
Sum4_In2_1210 = Switch2_Out1_1365;
|
325
|
-- sgn_In1_1429 = 30.0;
|
326
|
Khdgrte_In1_1131 = Sum1_Out1_1181;
|
327
|
Min_In1_1155 = Max_Out1_1147;
|
328
|
Logical_Operator_In1_1136 = HeadEng_Out1_69;
|
329
|
Khdg1_In1_1113 = Sum3_Out1_1201;
|
330
|
Khdg2_In1_1122 = Sum4_Out1_1211;
|
331
|
Max_In2_1146 = Khdg1_Out1_1114;
|
332
|
Min_In2_1156 = Khdg2_Out1_1123;
|
333
|
Max_In1_1145 = Khdgrte_Out1_1132;
|
334
|
Sum3_In2_1200 = rollLimitinput_Out1_79;
|
335
|
Sum4_In1_1209 = rollLimitinput_Out1_79;
|
336
|
-- Relational_Operator1_In1_1333 = sgn_Out1_1430;
|
337
|
-- Switch2_In1_1362 = sgn_Out1_1430;
|
338
|
-- Relational_Operator1_In1_1333 = -30.0;
|
339
|
-- Switch2_In1_1362 = -30.0;
|
340
|
Integrator1_1_In3_1304 = Roll_Out1_59;
|
341
|
Integrator1_1_In2_1303 = Logical_Operator_Out1_1137;
|
342
|
Switch3_In3_1373 = Min_Out1_1157;
|
343
|
Relational_Operator3_In1_1345 = Min_Out1_1157;
|
344
|
Relational_Operator2_In1_1339 = Min_Out1_1157;
|
345
|
-- Relational_Operator_In1_1327 = 30.0;
|
346
|
-- Switch1_In1_1353 = 30.0 ;
|
347
|
Logical_Operator1_2_In2_1316 = Relational_Operator1_Out1_1335;
|
348
|
Switch2_In2_1363 = Relational_Operator1_Out1_1335;
|
349
|
Switch2_In3_1364 = Switch1_Out1_1356;
|
350
|
Relational_Operator1_In2_1334 = Switch1_Out1_1356;
|
351
|
-- Relational_Operator3_In2_1346 = 0.0 ;
|
352
|
Logical_Operator1_2_In1_1315 = Relational_Operator3_Out1_1347;
|
353
|
Logical_Operator1_3_In2_1322 = Logical_Operator1_2_Out1_1317;
|
354
|
Logical_Operator1_3_In1_1321 = Logical_Operator1_1_Out1_1311;
|
355
|
Switch3_In2_1372 = Logical_Operator1_3_Out1_1323;
|
356
|
Logical_Operator1_1_In2_1310 = Relational_Operator2_Out1_1341;
|
357
|
-- Relational_Operator2_In2_1340 = 0.0;
|
358
|
-- Switch3_In1_1371 = 0.0 ;
|
359
|
Integrator1_1_In1_1302 = Switch3_Out1_1374;
|
360
|
Logical_Operator1_1_In1_1309 = Relational_Operator_Out1_1329;
|
361
|
Switch1_In2_1354 = Relational_Operator_Out1_1329;
|
362
|
Relational_Operator_In2_1328 = Integrator1_1_Out1_1305;
|
363
|
Switch1_In3_1355 = Integrator1_1_Out1_1305;
|
364
|
tel
|
365
|
|
366
|
|
367
|
|
368
|
node top ( HdgCmdMCP: real ; Heading : real ; psidot : real ; Vt : real ; Roll : real ; HeadEng : bool ; rollLimitInput : real )
|
369
|
returns (obs : bool);
|
370
|
var RollCmd : real;
|
371
|
let
|
372
|
|
373
|
RollCmd = HeadingControl ( HdgCmdMCP , Heading , psidot , Vt , Roll , HeadEng , rollLimitInput);
|
374
|
|
375
|
-- Put properties here
|
376
|
|
377
|
assert HeadEng;
|
378
|
|
379
|
assert (rollLimitInput > 0) and (rollLimitInput <= 30);
|
380
|
assert true -> (rollLimitInput = pre (rollLimitInput));
|
381
|
-- assert (Roll >= -rollLimitInput) and (Roll <= rollLimitInput);
|
382
|
|
383
|
obs = (RollCmd >= -rollLimitInput) and (RollCmd <= rollLimitInput);
|
384
|
|
385
|
--!MAIN : true;
|
386
|
--!PROPERTY: obs = true;
|
387
|
tel
|