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Revision 23b37f25

Added by Arnaud Dieumegard over 3 years ago

Concurrent signal assignment statement transformation to concurrent process statement

View differences:

src/backends/VHDL/vhdl_2_mini_vhdl_map.ml
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open Vhdl_ast
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open Mini_vhdl_ast
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open Vhdl_ast_fold_sensitivity
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type db_tuple_t =
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  {
......
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    mutable contexts: vhdl_load_t list;
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  }
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let get_sensitivity_list = object (self)
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  inherit ['acc] fold_sensitivity as super
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end
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let _ = fun (_ : vhdl_cst_val_t)  -> () 
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let _ = fun (_ : vhdl_type_t)  -> () 
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let _ = fun (_ : vhdl_element_declaration_t)  -> () 
......
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      fun x  ->
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        match x with
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        | VarAssign { label; lhs; rhs } ->
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            let label = self#lower_vhdl_name_t label  in
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            let lhs = self#lower_vhdl_name_t lhs  in
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            let rhs = self#vhdl_expr_t rhs  in VarAssign { label; lhs; rhs }
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        | SigSeqAssign { label; lhs; rhs } ->
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            let label = self#lower_vhdl_name_t label  in
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            let lhs = self#lower_vhdl_name_t lhs  in
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            let rhs = { expr = rhs; cond = None }::[] in
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            let rhs = self#list self#vhdl_waveform_element_t rhs in
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            SigSeqAssign { label; lhs; rhs }
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        | If { label; if_cases; default } ->
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            let label = self#lower_vhdl_name_t label  in
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            let if_cases = List.map self#vhdl_if_case_t if_cases  in
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            let default = List.map self#vhdl_sequential_stmt_t default  in
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            If { label; if_cases; default }
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        | Case { label; guard; branches } ->
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            let label = self#lower_vhdl_name_t label  in
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            let guard = self#vhdl_expr_t guard  in
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            let branches = List.map self#vhdl_case_item_t branches  in
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            Case { label; guard; branches }
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        | Exit { label; loop_label; condition } ->
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            let label = self#lower_vhdl_name_t label  in
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            let loop_label = self#option self#string loop_label  in
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            let condition = self#option self#vhdl_expr_t condition  in
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            Exit { label; loop_label; condition }
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        | Assert { label; cond; report; severity } ->
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            let label = self#lower_vhdl_name_t label  in
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            let cond = self#vhdl_expr_t cond  in
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            let report = self#vhdl_expr_t report  in
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            let severity = self#vhdl_expr_t severity  in
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            Assert { label; cond; report; severity }
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        | ProcedureCall { label; name; assocs } ->
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            let label = self#lower_vhdl_name_t label  in
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            let name = self#lower_vhdl_name_t name  in
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            let assocs = self#list self#vhdl_assoc_element_t assocs  in
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            ProcedureCall { label; name; assocs }
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        | Wait  -> Wait
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        | Null { label } ->
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            let label = self#lower_vhdl_name_t label  in Null { label }
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            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
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            Null { label }
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        | Return { label; expr } ->
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            let label = self#option self#lower_vhdl_name_t label  in
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            let expr = self#option self#vhdl_expr_t expr in
......
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        let declarations = List.map self#vhdl_declarative_item_t declarations  in
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        let active_sigs = self#list self#lower_vhdl_name_t active_sigs  in
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        let body = List.map self#vhdl_sequential_stmt_t body  in
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        { id; declarations; active_sigs; body }
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        let postponed = false in
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        let label = None in
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        { id; declarations; active_sigs; body; postponed; label }
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    method vhdl_selected_signal_t :
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      vhdl_selected_signal_t -> vhdl_selected_signal_t=
......
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            Process {
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              id = self#postfix_flatten_vhdl_name_t a.lhs "__implicit_process";
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              declarations = [];
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              active_sigs = [];
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              body = (SigSeqAssign {
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                label = NoName;
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              active_sigs = get_sensitivity_list#vhdl_concurrent_stmt_t x []; (* TODO: Resolve sensitivity list from here *)
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              body = (SigCondAssign {
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                label = None;
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                lhs = a.lhs;
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                rhs = a.rhs;
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              })::[]
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                delay = match a.delay with | IsNull -> None | _ -> Some a.delay
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              })::[];
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              postponed = a.postponed;
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              label = match a.label with | NoName -> None | _ -> Some a.label
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            }
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        | Process a -> let a = self#vhdl_process_t a  in Process a
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        | SelectedSig a -> let a = self#vhdl_selected_signal_t a  in SelectedSig a (* TODO: convert to Process *)
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        | SelectedSig a -> 
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            Process {
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              id = self#postfix_flatten_vhdl_name_t a.lhs "__implicit_process";
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              declarations = [];
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              active_sigs = get_sensitivity_list#vhdl_concurrent_stmt_t x []; (* TODO: Resolve sensitivity list from here *)
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              body = (SigSelectAssign {
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                label = None;
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                lhs = a.lhs;
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                sel = a.sel;
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                branches = a.branches;
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                delay = a.delay
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              })::[];
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              postponed = a.postponed;
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              label = match a.label with | NoName -> None | _ -> Some a.label
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            }
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        | ComponentInst a -> let a = self#vhdl_component_instantiation_t a  in ComponentInst a (* TODO: instantiate *)
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    method vhdl_port_t : vhdl_port_t -> vhdl_port_t=
......
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          contexts=contexts; 
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          declarations=declarations; 
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          definitions=definitions; 
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          body=body 
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          body=body (* TODO: Flatten component instantiation from here *)
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        }
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    method declarative_items_declarations : vhdl_declarative_item_t list -> vhdl_declaration_t list =

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