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Revision 23b37f25

Added by Arnaud Dieumegard over 3 years ago

Concurrent signal assignment statement transformation to concurrent process statement

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src/backends/VHDL/mini_vhdl_ast.ml
1 1
open Vhdl_ast
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type mini_vhdl_sequential_stmt_t = 
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  | VarAssign of { label: vhdl_name_t [@default NoName]; lhs: vhdl_name_t; rhs: vhdl_expr_t } [@name "VARIABLE_ASSIGNMENT_STATEMENT"]
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  | SigSeqAssign of { label: vhdl_name_t [@default NoName]; lhs: vhdl_name_t; rhs: vhdl_signal_condition_t list} [@name "SIGNAL_ASSIGNMENT_STATEMENT"]
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  | If of { label: vhdl_name_t [@default NoName]; if_cases: mini_vhdl_if_case_t list; default: mini_vhdl_sequential_stmt_t list [@default []]; } [@name "IF_STATEMENT"]
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  | Case of { label: vhdl_name_t [@default NoName]; guard: vhdl_expr_t; branches: mini_vhdl_case_item_t list } [@name "CASE_STATEMENT_TREE"]
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  | Exit of { label: vhdl_name_t [@default NoName]; loop_label: string option [@default Some ""]; condition: vhdl_expr_t option [@default Some IsNull]} [@name "EXIT_STATEMENT"]
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  | Assert of { label: vhdl_name_t [@default NoName]; cond: vhdl_expr_t; report: vhdl_expr_t [@default IsNull]; severity: vhdl_expr_t [@default IsNull]} [@name "ASSERTION_STATEMENT"]
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  | ProcedureCall of { label: vhdl_name_t [@default NoName]; name: vhdl_name_t; assocs: vhdl_assoc_element_t list [@default []] } [@name "PROCEDURE_CALL_STATEMENT"]
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  | Wait [@name "WAIT_STATEMENT"]
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  | Null of { label: vhdl_name_t [@default NoName]} [@name "NULL_STATEMENT"]
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  | Return of { label: vhdl_name_t option [@default None]; expr: vhdl_expr_t option [@default None]} [@name "RETURN_STATEMENT"]
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and mini_vhdl_if_case_t = 
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  | VarAssign of {
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      label: vhdl_name_t option;
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      lhs: vhdl_name_t;
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      rhs: vhdl_expr_t }
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  | SigSeqAssign of {
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      label: vhdl_name_t option;
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      lhs: vhdl_name_t;
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      rhs: vhdl_waveform_element_t list}
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  | SigCondAssign of {
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      label: vhdl_name_t option;
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      lhs: vhdl_name_t;
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      rhs: vhdl_signal_condition_t list;
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      delay: vhdl_expr_t option}
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  | SigSelectAssign of {
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      label: vhdl_name_t option;
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      lhs: vhdl_name_t;
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      sel: vhdl_expr_t;
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      branches: vhdl_signal_selection_t list;
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      delay: vhdl_expr_t option}
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  | If of {
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      label: vhdl_name_t option;
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      if_cases: mini_vhdl_if_case_t list;
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      default: mini_vhdl_sequential_stmt_t list}
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  | Case of {
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      label: vhdl_name_t option;
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      guard: vhdl_expr_t;
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      branches: mini_vhdl_case_item_t list }
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  | Exit of {
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      label: vhdl_name_t option;
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      loop_label: string option;
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      condition: vhdl_expr_t option}
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  | Assert of {
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      label: vhdl_name_t option;
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      cond: vhdl_expr_t;
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      report: vhdl_expr_t;
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      severity: vhdl_expr_t}
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  | ProcedureCall of {
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      label: vhdl_name_t option;
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      name: vhdl_name_t;
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      assocs: vhdl_assoc_element_t list }
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  | Wait
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  | Null of {
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      label: vhdl_name_t option}
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  | Return of {
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     label: vhdl_name_t option;
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     expr: vhdl_expr_t option}
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and mini_vhdl_if_case_t =
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  {
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    if_cond: vhdl_expr_t;
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    if_block: mini_vhdl_sequential_stmt_t list;
......
25 61

  
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type mini_vhdl_declaration_t =
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  | VarDecl of {
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : vhdl_expr_t [@default IsNull] 
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    } [@name "VARIABLE_DECLARATION"]
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  | CstDecl of { 
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      names : vhdl_name_t list;
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      typ : vhdl_subtype_indication_t;
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      init_val : vhdl_expr_t
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    } [@name "CONSTANT_DECLARATION"]
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  | SigDecl of { 
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      names : vhdl_name_t list; 
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      typ : vhdl_subtype_indication_t; 
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      init_val : vhdl_expr_t [@default IsNull]
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    } [@name "SIGNAL_DECLARATION"]
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    }
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  | CstDecl of {
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      names : vhdl_name_t list;
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      typ : vhdl_subtype_indication_t;
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      init_val : vhdl_expr_t
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    }
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  | SigDecl of {
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      names : vhdl_name_t list;
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      typ : vhdl_subtype_indication_t;
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      init_val : vhdl_expr_t
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    }
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  | ComponentDecl of {
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      name: vhdl_name_t [@default NoName];
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      generics: vhdl_port_t list [@default []];
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      ports: vhdl_port_t list [@default []];
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    } [@name "COMPONENT_DECLARATION"]
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      name: vhdl_name_t;
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      generics: vhdl_port_t list;
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      ports: vhdl_port_t list;
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    }
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  | Subprogram of {
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      spec: vhdl_subprogram_spec_t; 
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      decl_part: mini_vhdl_declaration_t list [@default []]; 
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      stmts: mini_vhdl_sequential_stmt_t list [@default []]
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    } [@name "SUBPROGRAM_BODY"]
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      spec: vhdl_subprogram_spec_t;
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      decl_part: mini_vhdl_declaration_t list;
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      stmts: mini_vhdl_sequential_stmt_t list
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    }
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[@@deriving show { with_path = false }];;
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type mini_vhdl_declarative_item_t =
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  {
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    use_clause: vhdl_load_t option [@default None];
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    declaration: mini_vhdl_declaration_t option [@default None];
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    definition: vhdl_definition_t option [@default None];
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    use_clause: vhdl_load_t option;
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    declaration: mini_vhdl_declaration_t option;
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    definition: vhdl_definition_t option;
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  }
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[@@deriving show { with_path = false }];;
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......
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    name: vhdl_name_t;
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    archi: vhdl_architecture_t;
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    entity: vhdl_entity_t;
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    generic_map: vhdl_assoc_element_t list [@default []];
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    port_map: vhdl_assoc_element_t list [@default []];
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    generic_map: vhdl_assoc_element_t list;
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    port_map: vhdl_assoc_element_t list;
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  }
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[@@deriving show { with_path = false }];;
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72 108
type mini_vhdl_process_t =
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  { 
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    id: vhdl_name_t [@default NoName];
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    declarations: mini_vhdl_declarative_item_t list [@key "PROCESS_DECLARATIVE_PART"] [@default []];
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    active_sigs: vhdl_name_t list [@default []];
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    body: mini_vhdl_sequential_stmt_t list [@key "PROCESS_STATEMENT_PART"] [@default []]
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  {
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    id: vhdl_name_t;
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    declarations: mini_vhdl_declarative_item_t list;
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    active_sigs: vhdl_name_t list;
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    body: mini_vhdl_sequential_stmt_t list;
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    postponed: bool;
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    label: vhdl_name_t option
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  }
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[@@deriving show { with_path = false }];;
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type mini_vhdl_concurrent_stmt_t =
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  | Process of mini_vhdl_process_t [@name "PROCESS_STATEMENT"]
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  | SelectedSig of vhdl_selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
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  | ComponentInst of mini_vhdl_component_instantiation_t [@name "COMPONENT_INSTANTIATION_STATEMENT"]
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  | Process of mini_vhdl_process_t
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  | SelectedSig of vhdl_selected_signal_t
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  | ComponentInst of mini_vhdl_component_instantiation_t
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[@@deriving show { with_path = false }];;
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type mini_vhdl_package_t =
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  {
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    name: vhdl_name_t [@default NoName];
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    shared_defs: vhdl_definition_t list [@default []];
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    shared_decls: mini_vhdl_declaration_t list [@default []];
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    shared_uses: vhdl_load_t list [@default []];
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    name: vhdl_name_t;
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    shared_defs: vhdl_definition_t list;
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    shared_decls: mini_vhdl_declaration_t list;
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    shared_uses: vhdl_load_t list;
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  }
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[@@deriving show { with_path = false }];;
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type mini_vhdl_component_t =
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  {
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    names: vhdl_name_t list [@default NoName];
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    generics: vhdl_port_t list [@default []]; (* From related 'entity' *)
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    ports: vhdl_port_t list [@default []]; (* From related 'entity' *)
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    contexts: vhdl_load_t list [@default []]; (* Related 'declarations' contexts + relatated entity contexts *)
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    declarations: mini_vhdl_declaration_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
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    definitions: vhdl_definition_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
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    body: mini_vhdl_concurrent_stmt_t list [@key "ARCHITECTURE_STATEMENT_PART"] [@default []]; (* + entity.stmts *)
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    names: vhdl_name_t list;
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    generics: vhdl_port_t list; (* From related 'entity' *)
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    ports: vhdl_port_t list; (* From related 'entity' *)
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    contexts: vhdl_load_t list; (* Related 'declarations' contexts + relatated entity contexts *)
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    declarations: mini_vhdl_declaration_t list; (* From inlined 'declarations' + entity.declaration *)
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    definitions: vhdl_definition_t list; (* From inlined 'declarations' + entity.declaration *)
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    body: mini_vhdl_concurrent_stmt_t list; (* + entity.stmts *)
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  }
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[@@deriving show { with_path = false }];;
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type mini_vhdl_design_file_t = 
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  {
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    components: mini_vhdl_component_t list [@default []];
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    packages: mini_vhdl_package_t list [@default []];
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    components: mini_vhdl_component_t list;
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    packages: mini_vhdl_package_t list;
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  }
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[@@deriving show { with_path = false }];;

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