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open Vhdl_ast
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open Mini_vhdl_ast
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let mini_vhdl_declaration_t_names decl=
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  match decl with
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  | SigDecl { names; typ; init_val } -> names
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  | _ -> []
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let rec remove_opt l=
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  match l with
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  | [] -> []
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  | (None)::tl -> remove_opt tl
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  | (Some a)::tl -> a::(remove_opt tl)
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let rec get_ports: vhdl_port_t list -> vhdl_port_mode_t -> vhdl_port_t list= 
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  fun l -> fun m -> match l with 
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    | [] -> [] 
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    | hd::tl -> if hd.port_mode = m then hd::(get_ports tl m) else get_ports tl m
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let rec get_ports_pos: vhdl_port_t list -> vhdl_port_mode_t -> int -> int list= 
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  fun l -> fun m -> fun index -> match l with 
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    | [] -> []
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    | hd::tl -> if hd.port_mode = m then index::(get_ports_pos tl m (index+1)) else get_ports_pos tl m (index+1)
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let get_names : vhdl_port_t -> vhdl_name_t list= fun x -> x.port_names
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let rec duplicates l1=
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  match l1 with
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  | [] -> []
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  | hd::tl -> if List.mem hd tl then hd::(duplicates (List.filter (fun x -> List.mem x tl) tl)) else duplicates tl
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let equals n1 n2=
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  match (n1,n2) with
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  | (Simple a, Identifier b) -> a = b
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  | (Identifier a, Simple b) -> a = b
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  | (Simple a, Selected ((Simple b)::[])) -> a = b
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  | (Simple a, Selected ((Identifier b)::[])) -> a = b
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  | (Identifier a, Selected ((Simple b)::[])) -> a = b
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  | (Identifier a, Selected ((Identifier b)::[])) -> a = b
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  | (Selected ((Simple b)::[]), Simple a) -> a = b
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  | (Selected ((Identifier b)::[]), Simple a) -> a = b
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  | (Selected ((Simple b)::[]), Identifier a) -> a = b
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  | (Selected ((Identifier b)::[]), Identifier a) -> a = b
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  | (a,b) -> a = b
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let find_vhdl_name_t l x =
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  let rec find_vhdl_name_t_aux x l index =
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    match l with
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    | [] -> -1
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    | hd::tl -> if (equals x hd) then index else find_vhdl_name_t_aux x tl (index+1) in
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  find_vhdl_name_t_aux x l 0
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let rec vhdl_name_t_mem x l =
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  match l with
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  | [] -> false
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  | hd::tl -> equals x hd || vhdl_name_t_mem x tl
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let rec diff l1 l2 =
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  match l1 with
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  | [] -> []
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  | hd::tl -> 
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      if vhdl_name_t_mem hd l2 then diff tl l2 else hd::(diff tl l2)
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let n_intersection ll =
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  let rec n_intersection_aux e_inter l = 
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    match e_inter with 
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    | [] -> l 
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    | hd::tl -> if (vhdl_name_t_mem hd l) then hd::(n_intersection_aux tl l) else n_intersection_aux tl l
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  in
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  List.fold_left n_intersection_aux [] ll
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let rec times : 'a list list -> 'a list list -> 'a list list=
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  fun a ->
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    fun b ->
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      match a with
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      | [] -> b
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      | hda::tla -> match b with
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                    | [] -> a
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                    | hdb::tlb -> [hdb@hda]@(times tla tlb)
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