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Revision 20d354f4

Added by Arnaud Dieumegard over 3 years ago

Update of types fields names

View differences:

src/backends/VHDL/vhdl_2_mini_vhdl_map.ml
196 196
 *)
197 197
    val mutable db : db_tuple_t list = []
198 198
    val mutable db_current : db_tuple_t = {
199
      entity = { name = NoName; generics = []; ports = []; declaration = []; stmts = [] };
200
      architecture = { name = NoName; entity = NoName; declarations = []; body = [] };
199
      entity = { e_name = NoName; generics = []; ports = []; e_declaration = []; stmts = [] };
200
      architecture = { a_name = NoName; entity = NoName; a_declarations = []; a_body = [] };
201 201
      architecture_signals = [];
202 202
      architecture_ports = [];
203 203
      architecture_generics = [];
......
220 220
      fun x ->
221 221
        let rec find a dbl =
222 222
          match dbl with
223
          | [] -> failwith ("No matching tuple in DB for architecture [" ^ self#to_string_vhdl_name_t x.name ^ "]")
223
          | [] -> failwith ("No matching tuple in DB for architecture [" ^ self#to_string_vhdl_name_t x.a_name ^ "]")
224 224
          | e::tl -> if (e.architecture = a) then (e.entity, e.contexts) else find a tl in find x db
225 225

  
226 226
    method get_tuple_from_archi_and_entity_name : (vhdl_name_t * vhdl_name_t) -> db_tuple_t=
......
232 232
          | [] -> failwith ("No matching tuple in DB for architecture [" ^ self#to_string_vhdl_name_t a_name ^
233 233
                           "] and entity [" ^ self#to_string_vhdl_name_t e_name ^ "]")
234 234
          | e::tl -> 
235
              let inner_e_arch_name = self#simplify_name_t e.architecture.name in
236
              let inner_e_ent_name = self#simplify_name_t e.entity.name in
235
              let inner_e_arch_name = self#simplify_name_t e.architecture.a_name in
236
              let inner_e_ent_name = self#simplify_name_t e.entity.e_name in
237 237
              if ((inner_e_arch_name = a_name) && (inner_e_ent_name = e_name)) 
238 238
              then e 
239 239
              else find (a_name,e_name) tl in 
......
244 244
      fun ( entities_pair, filter_name ) ->
245 245
      let rec filter ep n = match ep with
246 246
      | [] -> failwith ("Impossible to find an entity with name [" ^ self#to_string_vhdl_name_t filter_name ^ "]")
247
      | (c,{name; generics; ports; declaration; stmts})::tl -> 
248
          if (name = n) then 
247
      | (c,{e_name; generics; ports; e_declaration; stmts})::tl -> 
248
          if (e_name = n) then 
249 249
            List.hd ep
250 250
          else filter (List.tl ep) n in
251 251
      filter entities_pair filter_name
......
259 259
    method declarative_items_declarations : vhdl_declarative_item_t list -> vhdl_declaration_t list =
260 260
      fun x ->
261 261
        match x with
262
        | {use_clause=_; declaration=Some a;definition=_}::tl -> a::(self#declarative_items_declarations tl)
262
        | {use_clause=_; di_declaration=Some a; di_definition=_}::tl -> a::(self#declarative_items_declarations tl)
263 263
        | _::tl -> self#declarative_items_declarations tl
264 264
        | [] -> []
265 265

  
266 266
    method declarative_items_definitions : vhdl_declarative_item_t list -> vhdl_definition_t list =
267 267
      fun x ->
268 268
        match x with
269
        | {use_clause=_; declaration=_;definition=Some a}::tl -> a::(self#declarative_items_definitions tl)
269
        | {use_clause=_; di_declaration=_; di_definition=Some a}::tl -> a::(self#declarative_items_definitions tl)
270 270
        | _::tl -> self#declarative_items_definitions tl
271 271
        | [] -> []
272 272

  
273 273
    method declarative_items_uses : vhdl_declarative_item_t list -> vhdl_load_t list =
274 274
      fun x ->
275 275
        match x with
276
        | {use_clause=Some a; declaration=_;definition=_}::tl -> a::(self#declarative_items_uses tl)
276
        | {use_clause=Some a; di_declaration=_; di_definition=_}::tl -> a::(self#declarative_items_uses tl)
277 277
        | _::tl -> self#declarative_items_uses tl
278 278
        | [] -> []
279 279
(******************
......
287 287
      fun x ->
288 288
        match x with
289 289
        | Process a -> List.sort_uniq compare (
290
            List.flatten (List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names a.body)
290
            List.flatten (List.map self#mini_vhdl_sequential_stmt_t_assigned_signals_names a.p_body)
291 291
          )
292 292
        | ComponentInst a ->
293 293
            let out_ports_positions = get_ports_pos a.entity.ports OutPort 0 in
......
324 324
    method mini_vhdl_concurrent_stmt_t_memories : vhdl_name_t list -> mini_vhdl_concurrent_stmt_t -> vhdl_name_t list=
325 325
      fun assigned_signals -> fun x ->
326 326
        match x with
327
        | Process a -> List.flatten (List.map (self#memories assigned_signals []) a.body)
327
        | Process a -> List.flatten (List.map (self#memories assigned_signals []) a.p_body)
328 328
        | ComponentInst a -> [] (* Nothing to be reported here as memories are checked for each component *)
329 329

  
330 330
    method memories: vhdl_name_t list -> vhdl_name_t list -> mini_vhdl_sequential_stmt_t -> vhdl_name_t list=
......
443 443

  
444 444
    method vhdl_element_declaration_t :
445 445
      vhdl_element_declaration_t -> vhdl_element_declaration_t=
446
      fun { names; definition }  ->
447
        let names = self#list self#lower_vhdl_name_t names  in
446
      fun { ed_names; definition }  ->
447
        let ed_names = self#list self#lower_vhdl_name_t ed_names  in
448 448
        let definition = self#vhdl_subtype_indication_t definition  in
449
        { names; definition }
449
        { ed_names; definition }
450 450

  
451 451
    method vhdl_subtype_indication_t :
452 452
      vhdl_subtype_indication_t -> vhdl_subtype_indication_t=
453
      fun { name; functionName; const }  ->
454
        let name = self#lower_vhdl_name_t name  in
453
      fun { si_name; functionName; const }  ->
454
        let si_name = self#lower_vhdl_name_t si_name  in
455 455
        let functionName = self#lower_vhdl_name_t functionName  in
456 456
        let const = self#vhdl_constraint_t const  in
457
        { name; functionName; const }
457
        { si_name; functionName; const }
458 458

  
459 459
    method vhdl_discrete_range_t :
460 460
      vhdl_discrete_range_t -> vhdl_discrete_range_t=
......
593 593
            let a = self#int a  in let b = self#int b  in SuffixRange (a, b)
594 594

  
595 595
    method vhdl_parameter_t : vhdl_parameter_t -> vhdl_parameter_t=
596
      fun { names; mode; typ; init_val }  ->
597
        let names = self#list self#lower_vhdl_name_t names  in
598
        let mode = self#list self#string mode  in
599
        let typ = self#vhdl_subtype_indication_t typ  in
596
      fun { parameter_names; parameter_mode; parameter_typ; init_val }  ->
597
        let parameter_names = self#list self#lower_vhdl_name_t parameter_names  in
598
        let parameter_mode = self#list self#string parameter_mode  in
599
        let parameter_typ = self#vhdl_subtype_indication_t parameter_typ  in
600 600
        let init_val = self#option self#vhdl_cst_val_t init_val  in
601
        { names; mode; typ; init_val }
601
        { parameter_names; parameter_mode; parameter_typ; init_val }
602 602

  
603 603
    method vhdl_subprogram_spec_t :
604 604
      vhdl_subprogram_spec_t -> vhdl_subprogram_spec_t=
605
      fun { name; subprogram_type; typeMark; parameters; isPure }  ->
606
        let name = self#string name  in
605
      fun { ss_name; subprogram_type; typeMark; parameters; isPure }  ->
606
        let ss_name = self#string ss_name  in
607 607
        let subprogram_type = self#string subprogram_type  in
608 608
        let typeMark = self#lower_vhdl_name_t typeMark  in
609 609
        let parameters = self#list self#vhdl_parameter_t parameters  in
610 610
        let isPure = self#bool isPure  in
611
        { name; subprogram_type; typeMark; parameters; isPure }
611
        { ss_name; subprogram_type; typeMark; parameters; isPure }
612 612

  
613 613
    method vhdl_sequential_stmt_t :
614 614
      vhdl_sequential_stmt_t -> mini_vhdl_sequential_stmt_t=
615 615
      fun x  ->
616 616
        match x with
617
        | VarAssign { label; lhs; rhs } ->
617
        | VarAssign { label; seqs_lhs; rhs } ->
618 618
            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
619
            let lhs = self#lower_vhdl_name_t lhs  in
619
            let lhs = self#lower_vhdl_name_t seqs_lhs  in
620 620
            let rhs = self#vhdl_expr_t rhs  in VarAssign { label; lhs; rhs }
621
        | SigSeqAssign { label; lhs; rhs } ->
621
        | SigSeqAssign { label; seqs_lhs; rhs } ->
622 622
            let label = match label with NoName -> None | _ -> Some (self#lower_vhdl_name_t label) in
623
            let lhs = self#lower_vhdl_name_t lhs  in
623
            let lhs = self#lower_vhdl_name_t seqs_lhs  in
624 624
            let rhs = self#list self#vhdl_waveform_element_t rhs in
625 625
            SigSeqAssign { label; lhs; rhs }
626 626
        | If { label; if_cases; default } ->
......
703 703

  
704 704
    method vhdl_declarative_item_t :
705 705
      vhdl_declarative_item_t -> mini_vhdl_declarative_item_t=
706
      fun { use_clause; declaration; definition }  ->
706
      fun { use_clause; di_declaration; di_definition }  ->
707 707
        let use_clause = self#option self#vhdl_load_t use_clause  in
708 708
        let declaration = 
709
          match declaration with
709
          match di_declaration with
710 710
          | None -> None
711 711
          | Some a -> Some (self#vhdl_declaration_t a) in
712
        let definition = self#option self#vhdl_definition_t definition  in
712
        let definition = self#option self#vhdl_definition_t di_definition  in
713 713
        { use_clause; declaration; definition }
714 714

  
715 715
    method vhdl_waveform_element_t :
716 716
      vhdl_waveform_element_t -> vhdl_waveform_element_t=
717
      fun { value; delay }  ->
717
      fun { value; we_delay }  ->
718 718
        let value = self#option self#vhdl_expr_t value  in
719
        let delay = self#option self#vhdl_expr_t delay  in { value; delay }
719
        let we_delay = self#option self#vhdl_expr_t we_delay  in { value; we_delay }
720 720

  
721 721
    method vhdl_signal_condition_t :
722 722
      vhdl_signal_condition_t -> vhdl_signal_condition_t=
723
      fun { expr; cond }  ->
724
        let expr = self#list self#vhdl_waveform_element_t expr  in
725
        let cond = self#option self#vhdl_expr_t cond  in { expr; cond }
723
      fun { sc_expr; cond }  ->
724
        let sc_expr = self#list self#vhdl_waveform_element_t sc_expr  in
725
        let cond = self#option self#vhdl_expr_t cond  in { sc_expr; cond }
726 726

  
727 727
    method vhdl_signal_selection_t :
728 728
      vhdl_signal_selection_t -> vhdl_signal_selection_t=
729
      fun { expr; when_sel }  ->
730
        let expr = self#list self#vhdl_waveform_element_t expr  in
729
      fun { ss_expr; when_sel }  ->
730
        let ss_expr = self#list self#vhdl_waveform_element_t ss_expr  in
731 731
        let when_sel = self#list self#vhdl_expr_t when_sel  in
732
        { expr; when_sel }
732
        { ss_expr; when_sel }
733 733

  
734 734
    method vhdl_conditional_signal_t :
735 735
      vhdl_conditional_signal_t -> vhdl_conditional_signal_t=
736
      fun { postponed; label; lhs; rhs; delay }  ->
737
        let postponed = self#bool postponed  in
738
        let label = self#lower_vhdl_name_t label  in
739
        let lhs = self#lower_vhdl_name_t lhs  in
736
      fun { cs_postponed; cs_label; cs_lhs; rhs; cs_delay }  ->
737
        let cs_postponed = self#bool cs_postponed  in
738
        let cs_label = self#lower_vhdl_name_t cs_label  in
739
        let cs_lhs = self#lower_vhdl_name_t cs_lhs  in
740 740
        let rhs = self#list self#vhdl_signal_condition_t rhs  in
741
        let delay = self#vhdl_expr_t delay  in
742
        { postponed; label; lhs; rhs; delay }
741
        let cs_delay = self#vhdl_expr_t cs_delay  in
742
        { cs_postponed; cs_label; cs_lhs; rhs; cs_delay }
743 743

  
744 744
    method vhdl_process_t : vhdl_process_t -> mini_vhdl_process_t=
745
      fun { id; declarations; active_sigs; body }  ->
745
      fun { id; p_declarations; active_sigs; p_body }  ->
746 746
        let id = self#lower_vhdl_name_t id  in
747
        let declarations = List.map self#vhdl_declarative_item_t declarations  in
747
        let p_declarations = List.map self#vhdl_declarative_item_t p_declarations  in
748 748
        let active_sigs = self#list self#lower_vhdl_name_t active_sigs  in
749
        let body = List.map self#vhdl_sequential_stmt_t body  in
749
        let p_body = List.map self#vhdl_sequential_stmt_t p_body  in
750 750
        (* TODO: Explicit memories *)
751 751
        let postponed = false in
752 752
        let label = None in
753
        { id; declarations; active_sigs; body; postponed; label }
753
        { id; p_declarations; active_sigs; p_body; postponed; label }
754 754

  
755 755
    method vhdl_selected_signal_t :
756 756
      vhdl_selected_signal_t -> vhdl_selected_signal_t=
757
      fun { postponed; label; lhs; sel; branches; delay }  ->
758
        let postponed = self#bool postponed  in
759
        let label = self#lower_vhdl_name_t label  in
760
        let lhs = self#lower_vhdl_name_t lhs  in
757
      fun { ss_postponed; ss_label; ss_lhs; sel; branches; ss_delay }  ->
758
        let ss_postponed = self#bool ss_postponed  in
759
        let ss_label = self#lower_vhdl_name_t ss_label  in
760
        let ss_lhs = self#lower_vhdl_name_t ss_lhs  in
761 761
        let sel = self#vhdl_expr_t sel  in
762 762
        let branches = self#list self#vhdl_signal_selection_t branches  in
763
        let delay = self#option self#vhdl_expr_t delay  in
764
        { postponed; label; lhs; sel; branches; delay }
763
        let ss_delay = self#option self#vhdl_expr_t ss_delay  in
764
        { ss_postponed; ss_label; ss_lhs; sel; branches; ss_delay }
765 765

  
766 766
    method vhdl_port_mode_t : vhdl_port_mode_t -> vhdl_port_mode_t=
767 767
      fun x  -> x
768 768

  
769 769
    method vhdl_component_instantiation_t :
770 770
      vhdl_component_instantiation_t -> mini_vhdl_component_instantiation_t=
771
        fun { name; inst_unit; inst_unit_type; archi_name; generic_map; port_map }  ->
772
        let name = self#lower_vhdl_name_t name  in
771
        fun { ci_name; inst_unit; inst_unit_type; archi_name; generic_map; port_map }  ->
772
        let ci_name = self#lower_vhdl_name_t ci_name  in
773 773
        let archi_name = self#option self#lower_vhdl_name_t archi_name  in
774 774
        let inst_unit = self#lower_vhdl_name_t inst_unit in
775 775
        let db_tuple = match archi_name with
776
          | None -> failwith ("Component [" ^ self#to_string_vhdl_name_t name ^ "] is not an entity")
776
          | None -> failwith ("Component [" ^ self#to_string_vhdl_name_t ci_name ^ "] is not an entity")
777 777
          | Some a -> self#get_tuple_from_archi_and_entity_name (a, inst_unit) in (* Get corresponding tuple in db *)
778 778
        let archi = db_tuple.architecture in
779 779
        let entity = db_tuple.entity in
780 780
        let generic_map = self#list self#vhdl_assoc_element_t generic_map  in
781 781
        let port_map = self#list self#vhdl_assoc_element_t port_map  in
782
        let port_t_names_proj : vhdl_port_t -> vhdl_name_t list= fun x -> x.names in
782
        let port_t_names_proj : vhdl_port_t -> vhdl_name_t list= fun x -> x.port_names in
783 783
        (* port_map resolution *)
784 784
        let entity_ports_names = List.flatten (List.map port_t_names_proj entity.ports) in
785 785
        let port_map = self#vhdl_assoc_element_t_resolve port_map entity_ports_names in
786 786
        (* generic_map resolution *)
787 787
        let entity_generics_names = List.flatten (List.map port_t_names_proj entity.generics) in
788 788
        let generic_map = self#vhdl_assoc_element_t_resolve generic_map entity_generics_names in
789
        { name; archi; entity; generic_map; port_map }
789
        { ci_name; archi; entity; generic_map; port_map }
790 790

  
791 791
    method vhdl_concurrent_stmt_t :
792 792
      vhdl_concurrent_stmt_t -> mini_vhdl_concurrent_stmt_t=
......
794 794
        match x with
795 795
        | SigAssign a -> 
796 796
            Process {
797
              id = self#postfix_flatten_vhdl_name_t a.lhs "__implicit_process";
798
              declarations = [];
797
              id = self#postfix_flatten_vhdl_name_t a.cs_lhs "__implicit_process";
798
              p_declarations = [];
799 799
              active_sigs = get_sensitivity_list#vhdl_concurrent_stmt_t x [];
800
              body = (SigCondAssign {
800
              p_body = (SigCondAssign {
801 801
                label = None;
802
                lhs = a.lhs;
802
                lhs = a.cs_lhs;
803 803
                rhs = a.rhs;
804
                delay = match a.delay with | IsNull -> None | _ -> Some a.delay
804
                delay = match a.cs_delay with | IsNull -> None | _ -> Some a.cs_delay
805 805
              })::[];
806
              postponed = a.postponed;
807
              label = match a.label with | NoName -> None | _ -> Some a.label
806
              postponed = a.cs_postponed;
807
              label = match a.cs_label with | NoName -> None | _ -> Some a.cs_label
808 808
            }
809 809
        | Process a -> let a = self#vhdl_process_t a  in Process a
810 810
        | SelectedSig a -> 
811 811
            Process {
812
              id = self#postfix_flatten_vhdl_name_t a.lhs "__implicit_process";
813
              declarations = [];
812
              id = self#postfix_flatten_vhdl_name_t a.ss_lhs "__implicit_process";
813
              p_declarations = [];
814 814
              active_sigs = get_sensitivity_list#vhdl_concurrent_stmt_t x [];
815
              body = (SigSelectAssign {
815
              p_body = (SigSelectAssign {
816 816
                label = None;
817
                lhs = a.lhs;
817
                lhs = a.ss_lhs;
818 818
                sel = a.sel;
819 819
                branches = a.branches;
820
                delay = a.delay
820
                delay = a.ss_delay
821 821
              })::[];
822
              postponed = a.postponed;
823
              label = match a.label with | NoName -> None | _ -> Some a.label
822
              postponed = a.ss_postponed;
823
              label = match a.ss_label with | NoName -> None | _ -> Some a.ss_label
824 824
            }
825 825
        | ComponentInst a -> let a = self#vhdl_component_instantiation_t a  in ComponentInst a
826 826

  
827 827
    method vhdl_port_t : vhdl_port_t -> vhdl_port_t=
828
      fun { names; mode; typ; expr }  ->
829
        let names = self#list self#lower_vhdl_name_t names  in
830
        let mode = self#vhdl_port_mode_t mode  in
831
        let typ = self#vhdl_subtype_indication_t typ  in
832
        let expr = self#vhdl_expr_t expr  in { names; mode; typ; expr }
828
      fun { port_names; port_mode; port_typ; port_expr }  ->
829
        let port_names = self#list self#lower_vhdl_name_t port_names  in
830
        let port_mode = self#vhdl_port_mode_t port_mode  in
831
        let port_typ = self#vhdl_subtype_indication_t port_typ  in
832
        let port_expr = self#vhdl_expr_t port_expr  in { port_names; port_mode; port_typ; port_expr }
833 833

  
834 834
    method vhdl_entity_t : vhdl_entity_t -> unit =
835
      fun { name; generics; ports; declaration; stmts }  -> ()
835
      fun { e_name; generics; ports; e_declaration; stmts }  -> ()
836 836

  
837 837
    method vhdl_package_t : (vhdl_load_t list * vhdl_package_t) -> mini_vhdl_package_t=
838
      fun ( ctxs, {name; shared_defs; shared_decls; shared_uses })  ->
839
        let name = self#lower_vhdl_name_t name  in
838
      fun ( ctxs, {p_name; shared_defs; shared_decls; shared_uses })  ->
839
        let p_name = self#lower_vhdl_name_t p_name  in
840 840
        let shared_defs = self#list self#vhdl_definition_t shared_defs  in
841 841
        let shared_decls = List.map self#vhdl_declaration_t shared_decls  in
842 842
        let shared_uses = self#list self#vhdl_load_t shared_uses @ ctxs in
843
        { name; shared_defs; shared_decls; shared_uses }
843
        { p_name; shared_defs; shared_decls; shared_uses }
844 844

  
845 845
    method vhdl_load_t : vhdl_load_t -> vhdl_load_t=
846 846
      fun x  ->
......
853 853
                                  (vhdl_load_t list * vhdl_configuration_t) list *
854 854
                                  (vhdl_load_t list * vhdl_architecture_t)) -> mini_vhdl_component_t=
855 855
      fun ( packs_pairs, ents_pairs, confs_pairs, (arch_ctx, arch) ) ->
856
        let names = arch.name::(arch.entity::[])  in
856
        let names = arch.a_name::(arch.entity::[])  in
857 857
        let (ref_ent_ctx,ref_ent) = self#filter_entity (ents_pairs, arch.entity) in
858 858
        let contexts =
859 859
          ref_ent_ctx @ (* Referenced entity context elements *)
860 860
          arch_ctx @ (* Architecture context elements *)
861
          self#declarative_items_uses ref_ent.declaration @ (* Referenced entity inner context elements *)
862
          self#declarative_items_uses arch.declarations in (* Architecture inner context elements *)
861
          self#declarative_items_uses ref_ent.e_declaration @ (* Referenced entity inner context elements *)
862
          self#declarative_items_uses arch.a_declarations in (* Architecture inner context elements *)
863 863
        let declarations = 
864
          self#declarative_items_declarations ref_ent.declaration @ (* Referenced entity inner declarations *)
865
          self#declarative_items_declarations arch.declarations in (* Architecture inner declarations *)
864
          self#declarative_items_declarations ref_ent.e_declaration @ (* Referenced entity inner declarations *)
865
          self#declarative_items_declarations arch.a_declarations in (* Architecture inner declarations *)
866 866
        let definitions =
867
          self#declarative_items_definitions ref_ent.declaration @ (* Referenced entity inner definitions *)
868
          self#declarative_items_definitions arch.declarations in (* Architecture inner definitions *)
869
        let body = 
867
          self#declarative_items_definitions ref_ent.e_declaration @ (* Referenced entity inner definitions *)
868
          self#declarative_items_definitions arch.a_declarations in (* Architecture inner definitions *)
869
        let c_body = 
870 870
          List.map self#vhdl_concurrent_stmt_t ref_ent.stmts @ (* Referenced entity concurrent statement *)
871
          List.map self#vhdl_concurrent_stmt_t arch.body in (* Architecture concurrent statements *)
871
          List.map self#vhdl_concurrent_stmt_t arch.a_body in (* Architecture concurrent statements *)
872 872
        let generics = ref_ent.generics in (* Referenced entity generics *)
873 873
        let ports = ref_ent.ports in (* Referenced entity ports *)
874
        let declarations = List.map self#vhdl_declaration_t declarations in
874
        let c_declarations = List.map self#vhdl_declaration_t declarations in
875 875
        let (signals, subprograms) = 
876
          let rec find_decls declarations acc_s acc_p = 
877
            match declarations with
876
          let rec find_decls c_declarations acc_s acc_p = 
877
            match c_declarations with
878 878
            | [] -> (acc_s, acc_p)
879 879
            | (SigDecl (s))::tl -> find_decls tl ((SigDecl (s))::acc_s) (acc_p)
880 880
            | (Subprogram (s))::tl -> find_decls tl (acc_s) ((Subprogram (s))::acc_p)
881
            | _::tl -> find_decls tl acc_s acc_p in find_decls declarations [] [] in
882
        let assigned_signals_names = List.flatten (List.map self#mini_vhdl_concurrent_stmt_t_assigned_signals_names body) in
881
            | _::tl -> find_decls tl acc_s acc_p in find_decls c_declarations [] [] in
882
        let assigned_signals_names = List.flatten (List.map self#mini_vhdl_concurrent_stmt_t_assigned_signals_names c_body) in
883 883
        let functions = List.map (
884
          fun x -> match x with Subprogram (s) -> (Simple s.spec.name, s.spec.parameters, s.spec.typeMark) | _ -> failwith "Unreachable error (map on subprograms)"
884
          fun x -> match x with Subprogram (s) -> (Simple s.spec.ss_name, s.spec.parameters, s.spec.typeMark) | _ -> failwith "Unreachable error (map on subprograms)"
885 885
        ) subprograms in
886
        let memories = List.flatten (List.map (self#mini_vhdl_concurrent_stmt_t_memories assigned_signals_names) body) in
886
        let memories = List.flatten (List.map (self#mini_vhdl_concurrent_stmt_t_memories assigned_signals_names) c_body) in
887 887
        let new_tuple = { entity=ref_ent; 
888 888
                          architecture=arch; 
889 889
                          architecture_signals=signals;
......
895 895
                          contexts=contexts } in
896 896
        self#db_add_tuple new_tuple;
897 897
        self#db_set_current new_tuple;
898
        { names; generics=generics; ports=ports; contexts=contexts; declarations=declarations; definitions=definitions; body=body }
898
        { names; generics=generics; ports=ports; contexts=contexts; c_declarations=c_declarations; definitions=definitions; c_body=c_body }
899 899

  
900 900
    method vhdl_configuration_t :
901 901
      vhdl_configuration_t -> unit= self#unit
......
928 928
*)
929 929

  
930 930
    method sndpass_mini_vhdl_component_t : mini_vhdl_component_t -> mini_vhdl_component_t=
931
      fun { names; generics; ports; contexts; declarations; definitions; body } ->
931
      fun { names; generics; ports; contexts; c_declarations; definitions; c_body } ->
932 932
        (* TODO: resolve association list for function/procedures calls *)
933
      { names; generics; ports; contexts; declarations; definitions; body }
933
      { names; generics; ports; contexts; c_declarations; definitions; c_body }
934 934

  
935 935
    method sndpass_mini_vhdl_design_file_t : mini_vhdl_design_file_t -> mini_vhdl_design_file_t=
936 936
      fun { components; packages } ->

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