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Revision 1e0f3191

Added by Arnaud Dieumegard almost 4 years ago

Update of types fields names

View differences:

src/tools/importer/mini_vhdl_to_lustre.ml
38 38
        let node_clock = Clocks.new_ck Cvar false in
39 39
        let in_ports = Mini_vhdl_utils.get_ports ports InPort in
40 40
        let inports_names = List.map Mini_vhdl_utils.get_names in_ports in
41
        let inports_types = List.map (fun x -> x.typ) in_ports in
41
        let inports_types = List.map (fun x -> x.port_typ) in_ports in
42 42
        let node_inputs = List.flatten (List.map2 (self#lustre_mk_var_decl InPort) inports_names inports_types) in
43 43
        let out_ports = Mini_vhdl_utils.get_ports ports OutPort in
44 44
        let outports_names = List.map Mini_vhdl_utils.get_names out_ports in
45
        let outports_types = List.map (fun x -> x.typ) out_ports in
45
        let outports_types = List.map (fun x -> x.port_typ) out_ports in
46 46
        let node_outputs = List.flatten (List.map2 (self#lustre_mk_var_decl OutPort) outports_names outports_types) in
47 47
        (* TODO: deal with inout ports *)
48 48
        let body = List.map self#mini_vhdl_concurrent_stmt_t c_stmts in
......
80 80

  
81 81
    method vhdl_element_declaration_t :
82 82
      vhdl_element_declaration_t -> vhdl_element_declaration_t=
83
      fun { names; definition }  ->
83
      fun { ed_names; definition }  ->
84 84
        (*let names = self#list self#vhdl_name_t names  in
85 85
        let definition = self#vhdl_subtype_indication_t definition  in*)
86
        { names; definition }
86
        { ed_names; definition }
87 87

  
88 88
    method vhdl_subtype_indication_t :
89 89
      vhdl_subtype_indication_t -> Types.type_expr=
90
      fun { name; functionName; const }  ->
91
        let name = self#vhdl_name_t name  in
90
      fun { si_name; functionName; const }  ->
91
        let si_name = self#vhdl_name_t si_name  in
92 92
        (*let functionName = self#vhdl_name_t functionName  in
93 93
        let const = self#vhdl_constraint_t const  in*)
94
        let desc = match name with
94
        let desc = match si_name with
95 95
                  | "integer" -> Types.Tbasic (Tint)
96 96
                  | "boolean" -> Types.Tbasic (Tbool)
97
                  | _ -> Tconst (name) in
97
                  | _ -> Tconst (si_name) in
98 98
        Types.new_ty desc;
99 99

  
100 100
    method vhdl_subtype_indication_t_type_dec :
101 101
      vhdl_subtype_indication_t -> type_dec=
102
      fun { name; functionName; const }  ->
103
        let name = self#vhdl_name_t name  in
102
      fun { si_name; functionName; const }  ->
103
        let si_name = self#vhdl_name_t si_name  in
104 104
        (*let functionName = self#vhdl_name_t functionName  in
105 105
        let const = self#vhdl_constraint_t const  in*)
106
        {ty_dec_desc = Tydec_const name;
106
        {ty_dec_desc = Tydec_const si_name;
107 107
         ty_dec_loc = Location.dummy_loc }
108 108

  
109 109
    method vhdl_discrete_range_t :
......
379 379

  
380 380
    (* TODO : transform this as a new node *)
381 381
    method mini_vhdl_process_t : mini_vhdl_process_t -> mini_vhdl_process_t=
382
      fun { id; declarations; active_sigs; body; postponed; label }  ->
382
      fun { id; p_declarations; active_sigs; p_body; postponed; label }  ->
383 383
(*        let id = self#vhdl_name_t id  in
384 384
        let declarations =
385 385
          self#list self#mini_vhdl_declarative_item_t declarations  in
......
387 387
        let body = self#list self#mini_vhdl_sequential_stmt_t body  in
388 388
        let postponed = self#bool postponed  in
389 389
        let label = self#option self#vhdl_name_t label  in *)
390
        { id; declarations; active_sigs; body; postponed; label }
390
        { id; p_declarations; active_sigs; p_body; postponed; label }
391 391

  
392 392
    (* TODO : transform this as a node call *)
393 393
    method mini_vhdl_component_instantiation_t :
394 394
      mini_vhdl_component_instantiation_t -> statement=
395
      fun { name; archi; entity; generic_map; port_map }  ->
396
        let name = self#vhdl_name_t name  in
395
      fun { ci_name; archi; entity; generic_map; port_map }  ->
396
        let ci_name = self#vhdl_name_t ci_name  in
397 397
        (*let archi = archi  in
398 398
        let entity = entity  in
399 399
        let generic_map = self#list self#vhdl_assoc_element_t generic_map  in
400 400
        let port_map = self#list self#vhdl_assoc_element_t port_map  in*)
401
        Eq {eq_lhs=[name];
401
        Eq {eq_lhs=[ci_name];
402 402
            eq_rhs={expr_tag=Utils.new_tag (); expr_desc=Expr_ident "toto";
403 403
                    expr_type={tdesc=Tconst "cst"; tid=0}; expr_clock={cdesc=Cvar;cscoped=false;cid=0};
404 404
                    expr_delay={ddesc=Dundef;did=0}; expr_annot=None; expr_loc=Location.dummy_loc};
......
419 419
            let a = self#mini_vhdl_component_instantiation_t a  in a
420 420

  
421 421
    method mini_vhdl_package_t : mini_vhdl_package_t -> top_decl_desc=
422
      fun { name; shared_defs; shared_decls; shared_uses }  ->
423
        let node_id = self#vhdl_name_t name  in
422
      fun { p_name; shared_defs; shared_decls; shared_uses }  ->
423
        let node_id = self#vhdl_name_t p_name  in
424 424
        (*let shared_defs = self#list self#vhdl_definition_t shared_defs  in
425 425
        let shared_decls = List.map self#mini_vhdl_declaration_t shared_decls  in
426 426
        let shared_uses = self#list self#vhdl_load_t shared_uses in*)
......
435 435
    method mini_vhdl_component_t :
436 436
      mini_vhdl_component_t -> top_decl_desc =
437 437
      fun
438
        { names; generics; ports; contexts; declarations; definitions; body }
438
        { names; generics; ports; contexts; c_declarations; definitions; c_body }
439 439
         ->
440 440
        (*let generics = self#list self#vhdl_port_t generics  in*)
441 441
        let ports = self#list self#vhdl_port_t ports  in
442 442
        (*let contexts = self#list self#vhdl_load_t contexts  in*)
443
        let declarations = List.flatten (List.map self#mini_vhdl_declaration_t declarations) in
443
        let c_declarations = List.flatten (List.map self#mini_vhdl_declaration_t c_declarations) in
444 444
        (*let definitions = List.map self#vhdl_definition_t definitions  in (* TODO: add the result of this transformation to mk_node call *)
445 445
        let node_id = String.concat "__" (List.map show_vhdl_name_t names) in
446 446
        let node_type = Types.new_var () in
447 447
        let node_clock = Clocks.new_ck Cvar false in*)
448
        self#lustre_mk_node names declarations ports body
448
        self#lustre_mk_node names c_declarations ports c_body
449 449

  
450 450
    method mini_vhdl_design_file_t :
451 451
      mini_vhdl_design_file_t -> program_t =

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