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1
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open Vhdl_ast
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2
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3
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let design1 = {
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4
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packages = [{name = "typedef"; shared_defs = [Subtype{name = "byte"; definition = Bit_vector (7, 0)}]}];
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5
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libraries = [Use ["work";"typedef";"all"]];
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6
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entities = [{ name = "data_path";
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7
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generics = [];
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8
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ports = [
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9
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{name = "clk"; kind = InPort; typ = Base "boolean"};
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10
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{name = "rst"; kind = InPort; typ = Base "boolean"};
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11
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{name = "s_1"; kind = InPort; typ = Base "boolean"};
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12
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{name = "s0"; kind = InPort; typ = Base "bit"};
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13
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{name = "s1"; kind = InPort; typ = Base "bit"};
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14
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{name = "d0"; kind = InPort; typ = Base "byte"};
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15
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{name = "d1"; kind = InPort; typ = Base "byte"};
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16
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{name = "d2"; kind = InPort; typ = Base "byte"};
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17
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{name = "d3"; kind = InPort; typ = Base "byte"};
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18
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{name = "q"; kind = OutPort; typ = Base "byte"};
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19
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20
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];
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21
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}];
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22
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architectures = [{
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23
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name = "behavior";
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24
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entity = "data_path";
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25
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declarations = [
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26
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SigDecl { name = "reg"; typ = Base "byte"; init_val = None};
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27
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SigDecl { name = "shft"; typ = Base "byte"; init_val = None};
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28
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SigDecl { name = "sel"; typ = Bit_vector(1,0); init_val = None};
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29
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30
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];
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31
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body = [
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32
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Process {
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33
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id = None;
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34
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active_sigs = ["clk"; "rst"];
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35
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body = [
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36
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If {
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37
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if_cases = [
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38
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{
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39
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if_cond = Sig{ name = "rst"; att = None };
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40
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if_block = [
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41
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SigSeqAssign { lhs = "req"; rhs = Cst (CstBV("x", "00"))};
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42
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SigSeqAssign { lhs = "shft"; rhs = Cst (CstBV("x", "00"))};
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43
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];
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44
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};
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45
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{
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46
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if_cond = Op {id = "and"; args = [Sig{ name = "clk"; att = None };
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47
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Sig{ name = "clk"; att = Some (SigAtt "event") }]};
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48
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if_block = [
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49
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SigSeqAssign { lhs = "req"; rhs = Op { id = "&"; args = [
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50
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Sig{ name = "s0"; att = None };
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51
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Sig{ name = "s1"; att = None }
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52
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]
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53
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}
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54
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};
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55
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Case {
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56
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guard = Sig{ name = "sel"; att = None };
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57
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branches = [
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58
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{
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59
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when_cond = Cst (CstBV("b", "00"));
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60
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when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d0"; att = None }};
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61
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};
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62
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{
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63
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when_cond = Cst (CstBV("b", "10"));
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64
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when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d1"; att = None }};
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65
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};
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66
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{
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67
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when_cond = Cst (CstBV("b", "01"));
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68
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when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d2"; att = None }};
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69
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};
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70
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{
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71
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when_cond = Cst (CstBV("b", "11"));
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72
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when_stmt = SigSeqAssign { lhs = "req"; rhs = Sig{ name = "d3"; att = None }};
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73
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};
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74
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75
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]
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76
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77
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};
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78
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If {
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79
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if_cases = [
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80
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{
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81
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if_cond = Sig{ name = "s_1"; att = None };
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82
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if_block = [
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83
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SigSeqAssign {
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84
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lhs = "shft";
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85
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rhs = Op { id = "&";
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86
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args = [
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87
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SuffixMod {
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88
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expr = Sig{ name = "shft"; att = None };
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89
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selection = Range (6,0);
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90
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};
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91
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SuffixMod {
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92
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expr = Sig{ name = "shft"; att = None };
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93
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selection = Idx 7;
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94
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}
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95
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]
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96
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}
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97
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};
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98
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];
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99
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};
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100
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];
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101
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default = Some [
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102
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SigSeqAssign { lhs = "shft"; rhs = Var "reg"};
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103
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]
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104
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};
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105
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];
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106
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};
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107
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|
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108
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];
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109
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default = None;
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110
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}
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111
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];
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112
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};
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113
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SigAssign {
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114
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lhs = "q";
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115
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rhs = Var "shft";
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116
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cond = None;
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117
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}
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118
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|
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119
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];
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120
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}];
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121
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configuration = None;
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122
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}
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123
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