|
1
|
open Vhdl_ast
|
|
2
|
|
|
3
|
type mini_vhdl_component_instantiation_t =
|
|
4
|
{
|
|
5
|
name: vhdl_name_t;
|
|
6
|
archi: vhdl_architecture_t;
|
|
7
|
entity: vhdl_entity_t;
|
|
8
|
generic_map: vhdl_assoc_element_t list [@default []];
|
|
9
|
port_map: vhdl_assoc_element_t list [@default []];
|
|
10
|
}
|
|
11
|
[@@deriving show { with_path = false }];;
|
|
12
|
|
|
13
|
type mini_vhdl_concurrent_stmt_t =
|
|
14
|
| SigAssign of vhdl_conditional_signal_t [@name "CONDITIONAL_SIGNAL_ASSIGNMENT"]
|
|
15
|
| Process of vhdl_process_t [@name "PROCESS_STATEMENT"]
|
|
16
|
| SelectedSig of vhdl_selected_signal_t [@name "SELECTED_SIGNAL_ASSIGNMENT"]
|
|
17
|
| ComponentInst of mini_vhdl_component_instantiation_t [@name "COMPONENT_INSTANTIATION_STATEMENT"]
|
|
18
|
[@@deriving show { with_path = false }];;
|
|
19
|
|
|
20
|
type mini_vhdl_component_t =
|
|
21
|
{
|
|
22
|
names: vhdl_name_t list [@default NoName];
|
|
23
|
generics: vhdl_port_t list [@default []]; (* From related 'entity' *)
|
|
24
|
ports: vhdl_port_t list [@default []]; (* From related 'entity' *)
|
|
25
|
contexts: vhdl_load_t list [@default []]; (* Related 'declarations' contexts + relatated entity contexts *)
|
|
26
|
declarations: vhdl_declaration_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
|
|
27
|
definitions: vhdl_definition_t list [@default []]; (* From inlined 'declarations' + entity.declaration *)
|
|
28
|
body: mini_vhdl_concurrent_stmt_t list [@key "ARCHITECTURE_STATEMENT_PART"] [@default []]; (* + entity.stmts *)
|
|
29
|
}
|
|
30
|
[@@deriving show { with_path = false }];;
|
|
31
|
|
|
32
|
type mini_vhdl_design_file_t =
|
|
33
|
{
|
|
34
|
components: mini_vhdl_component_t list [@default []];
|
|
35
|
packages: vhdl_package_t list [@default []];
|
|
36
|
}
|
|
37
|
[@@deriving show { with_path = false }];;
|