CristalCaveGem » LustreC

Added polymorphic option for generated visitors

Résolutions de conflits

Labels are now optional in the VHDL ast

Removed warnings and solved bug for visitors iterators references between vhdl_ast and mini_vhdl_ast

Making labels optional for sequential statements

Beggining of implicit latching check

Updated expression folding visitor using visitors ppx

Removed generated yojson parser, now relies on pre-processed version

Update of types fields names

Merged separated types as one type for VHDL and MiniVHDL asts

Comments update

vhdl and mini_vhdl pp: remove empty lines and useless linebreaks in maps

Added missing Open pattern matching case

Extraction of signals assignments in component instantiation concurrent statements

Added Open vhdl_name_t case in pattern matchings

Beginning of squeleton for mini_vhdl refactoring

vhdl 2 mini-vhdl code cleaning

First version of implicit memories explicitation

Mini vhdl utils simplification

Added open in vhdl ast

Vhdl yojson parsing/printing (open)

Vhdl pp update (open)

Mini vhdl pp update (If, Case, Use clause)

component instantiation generic map resolution

Bug fix: pp for unary operations

Resolution of association lists for component instantiation

Communalisation of mini-vhdl structure utils

Code cleaning in vhdl to mini-vhdl transformation

Added missing sensitivity list resolution fold

DB tuple update to contain assigned elements in component

vhdl and mini-vhdl process printing

Removed concurrent assignment statement from mini-vhdl grammar

Mini-vhdl pretty printing for sequential statements and processes

Concurrent signal assignment statement transformation to concurrent process statement

Clean ppx deriving comments

Update of mini-vhdl pp

Building explicit process from concurrent signl assignment

Bug fix: resolve entity/arch reference from component instantiation declaration

Start of the Lustre generator

mutable object field storing architecture<->entities<->contexts relation, generation of MiniVHDL component instantiation

Added MiniVHDL versions of component instantiation and concurretn statement

PP order for components and packages

PP for packages in minivhdl

Typo correction

Some code comments

definition of the mini-vhdl types + pp + transformation from vhdl structure

Split PP and Yojson in separate ml for vhdl ast

PP update: component instantiation type, archi format, port & generic decl in components, signal conditions, return statements expression

Printer corrections: signal_condition, conditional_signal, elsif, when conditions, F***ing non-brekaing characters

PP for procedure call

Qualified expressions, default values for expressions, pp for association_elements

Unbounded array definition printing

Use clauses in package definition

Conditional signals selection, waveform with delay

PP for Subprogram

Correction of Procedure declaration pp

Default value for ProcedureCall assocs

Aggregate pp, correction of element_assoc pp

Default value corrections

Added support for declarative items

Added support for use clause in architecture declarations

Update of component instantiation pp

Corrections on component instantiation

Added support for Component declarations in packages

Pretty printing of assert statements

Constant expression printing with units, Format for case statements, process formatting and name

Added support for constants units

Added support for Array,Record,Enumeration constructs

Added support for ProcedureCall statements

Update of the component instantiation type to add architecture name reference

Added support for component instantiation

code cleaning

Correction of Variables,Signals,Constants definitions of initial values. Now uses an expression.

PP correction for separating spaces

PP support for concurrent assignment, processes

PP for Exit, Null and Return statements

Update of default values for some option constructions + added end if and end case closing of if and case blocks

Update of the vhdl pretty printer

New version of the vhdl import + compilation

Working example!

Pom pom pom

Sample value for VHDL

Compiling - while doing nothing :)

Bootstrapping VHDL importer/exporter