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lustrec / src / tools / importer @ 13872a54

# Date Author Comment
13872a54 09/25/2018 03:56 PM Arnaud Dieumegard

Added missing transformation methods squelettons for mini_vhdl to lustre transformation

d040e852 09/10/2018 04:36 PM Arnaud Dieumegard

Modified output display for check mode

e15a8d65 08/31/2018 10:05 AM Arnaud Dieumegard

Added open in vhdl ast

a16d29bf 08/29/2018 04:29 PM Arnaud Dieumegard

Communalisation of mini-vhdl structure utils

70836642 08/28/2018 03:52 PM Arnaud Dieumegard

Updated checks display and adde small obvious checks

a33a345a 08/27/2018 05:36 PM Arnaud Dieumegard

Added -check flag to start vhdl model verification

b6ff3e98 08/27/2018 02:42 PM Arnaud Dieumegard

Removed concurrent assignment statement from mini-vhdl grammar

304640aa 08/24/2018 04:52 PM Arnaud Dieumegard

update of mini-vhdl to lustre

4a0ba157 08/24/2018 01:49 PM Arnaud Dieumegard

Minor comments update

1732ef44 07/31/2018 02:35 PM Arnaud Dieumegard

Start of the Lustre generator

b15439da 07/30/2018 06:04 PM Arnaud Dieumegard

Update of the command line

cd7d074b 07/30/2018 05:33 PM Arnaud Dieumegard

Added command line parameters

5bbf7413 07/30/2018 03:59 PM Arnaud Dieumegard

definition of the mini-vhdl types + pp + transformation from vhdl structure

58f8ddf5 07/27/2018 04:23 PM Arnaud Dieumegard

Split PP and Yojson in separate ml for vhdl ast

b0c77300 07/26/2018 06:05 PM Arnaud Dieumegard

PP update: component instantiation type, archi format, port & generic decl in components, signal conditions, return statements expression

1f593d5d 07/26/2018 03:12 PM Arnaud Dieumegard

Printer corrections: signal_condition, conditional_signal, elsif, when conditions, F***ing non-brekaing characters

7f5d0cde 07/25/2018 04:01 PM Arnaud Dieumegard

Qualified expressions, default values for expressions, pp for association_elements

d4c98bae 07/25/2018 11:42 AM Arnaud Dieumegard

Use clauses in package definition

d3a35600 07/25/2018 11:29 AM Arnaud Dieumegard

Conditional signals selection, waveform with delay

3d099916 07/24/2018 04:49 PM Arnaud Dieumegard

PP for Subprogram

7f55f63f 07/24/2018 02:35 PM Arnaud Dieumegard

Default value corrections

ec031ed0 07/24/2018 01:31 PM Arnaud Dieumegard

Added support for declarative items

77bdbec5 07/24/2018 10:53 AM Arnaud Dieumegard

Added support for use clause in architecture declarations

44998c1e 07/23/2018 05:59 PM Arnaud Dieumegard

Corrections on component instantiation

3b8ba4b5 07/23/2018 04:58 PM Arnaud Dieumegard

Added support for Component declarations in packages

ab6312e7 07/23/2018 02:54 PM Arnaud Dieumegard

Added support for constants units

ac6b9224 07/23/2018 01:54 PM Arnaud Dieumegard

Main executable now throws exceptions when parsing errors

248eb65e 07/23/2018 01:54 PM Arnaud Dieumegard

Added support for Array,Record,Enumeration constructs

6d3b5007 07/20/2018 04:52 PM Arnaud Dieumegard

Added support for ProcedureCall statements

6f9095f6 07/19/2018 05:42 PM Arnaud Dieumegard

Update of the component instantiation type to add architecture name reference

27332198 07/19/2018 01:40 PM Arnaud Dieumegard

Added support for component instantiation

4fda48d3 07/17/2018 04:01 PM Arnaud Dieumegard

Cleaned main importer, now outputs only the vhdl code

d4175560 07/17/2018 04:00 PM Arnaud Dieumegard

Correction of Variables,Signals,Constants definitions of initial values. Now uses an expression.

cfe98135 07/17/2018 10:42 AM Arnaud Dieumegard

Update of importer to display only last version of pretty printed vhdl code

40364f53 07/16/2018 10:44 AM Arnaud Dieumegard

New version of the vhdl import + compilation

e1102543 07/11/2018 04:52 PM Arnaud Dieumegard

Renaming of cst_val_t type as vhdl_cst_val_t

d3f0059e 07/11/2018 04:49 PM Arnaud Dieumegard

New version of the VHDL importer with pretty printing based on ppx_show

62b6a61c 07/11/2018 09:32 AM Arnaud Dieumegard

Functional VHDL importer

eb07b479 07/09/2018 05:05 PM Arnaud Dieumegard

Added support for subprograms, variables assignments, aggregate, others

fbc571e6 07/04/2018 04:06 PM Arnaud Dieumegard

Refactoring of vhdl data types

fae1790f 06/21/2018 05:42 PM Arnaud Dieumegard

Added support for Process statements, signal assignment, If, Exit and Null sequential statements

d77323b8 06/15/2018 05:45 PM Arnaud Dieumegard

Added postprocessing for numeric literals

55963629 06/12/2018 05:10 PM Arnaud Dieumegard

Ongoing work on json vhdl to vhdl structure conversion

3ca452f3 06/01/2018 04:12 PM Pierre-Loïc Garoche

Main lustrei