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lustrec / src / backends @ 6cfa0edc

# Date Author Comment
6cfa0edc 02/19/2019 12:47 PM Arnaud Dieumegard

MiniVHDL printer corrections

50fb3395 02/19/2019 09:42 AM Arnaud Dieumegard

Use clause printing correction

80adb7bd 01/07/2019 01:21 PM Arnaud Dieumegard

refactoring for utils and ast transformations

a73dd470 01/07/2019 01:20 PM Arnaud Dieumegard

Refactoring of utils

5cfb7200 01/04/2019 05:13 PM Arnaud Dieumegard

Initial commit for signals lattice building

ccd386cb 01/04/2019 03:54 PM Arnaud Dieumegard

Added on keywork for wait statement and removed is keywork in process definition when sensitivity list is empty

00b2e06b 01/04/2019 03:48 PM Arnaud Dieumegard

rewriting of processes to transform sensitivity list to wait on statement

bd1f1929 01/04/2019 03:46 PM Arnaud Dieumegard

Added sensitivity list to Wait statements in VHDL and MiniVHDL

4515d925 01/04/2019 03:00 PM Arnaud Dieumegard

Added MiniVHDL package pp

e0f0bc2c 01/04/2019 02:54 PM Arnaud Dieumegard

Added polymorphic option for generated visitors

c26f5a31 01/04/2019 02:45 PM Arnaud Dieumegard

Résolutions de conflits

c1b877b6 01/04/2019 02:40 PM Arnaud Dieumegard

Labels are now optional in the VHDL ast

92aface4 12/14/2018 03:02 PM Arnaud Dieumegard

Removed warnings and solved bug for visitors iterators references between vhdl_ast and mini_vhdl_ast

265f2eca 12/12/2018 11:11 AM Arnaud Dieumegard

Making labels optional for sequential statements

5360dcf8 12/07/2018 05:50 PM Arnaud Dieumegard

Beggining of implicit latching check

aeec0f04 12/07/2018 11:08 AM Arnaud Dieumegard

Updated expression folding visitor using visitors ppx

e050e30c 12/06/2018 12:41 PM Arnaud Dieumegard

Removed generated yojson parser, now relies on pre-processed version

20d354f4 12/06/2018 12:40 PM Arnaud Dieumegard

Update of types fields names

95076858 12/06/2018 12:39 PM Arnaud Dieumegard

Merged separated types as one type for VHDL and MiniVHDL asts

92c6cca7 11/17/2018 04:54 AM Pierre-Loïc Garoche

Merge branch 'lustrec-seal' into vhdl

b59fa954 11/17/2018 02:04 AM Pierre-Loïc Garoche

Merge branch 'unstable' into vhdl

59803095 11/16/2018 11:30 PM Pierre-Loïc Garoche

Merge branch 'unstable' into lustrec-seal

d948c0bd 11/16/2018 04:18 AM Pierre-Loïc Garoche

math fun lib support in MPFR

ae7d913d 11/16/2018 04:18 AM Pierre-Loïc Garoche

Merlin files

45d53dc3 11/16/2018 02:46 AM Pierre-Loïc Garoche

EMF export of local type definition (for simple types)

c35de73b 11/15/2018 03:18 AM Pierre-Loïc Garoche

Pretty serious update:
- a bug in regressio ntest Simulink/integrator_ext_IC_matrix_test revealed the following (serious issue):
when building the list of instruction (in the machine code) the access to variable were hardcoded to LocalVar or StateVAr depending whether the variables was part of the identified memories....

0d54d8a8 11/13/2018 02:01 AM Pierre-Loïc Garoche

Removed Contract contruct: imported node should be enough. Solved some warning at compile time

99cb0623 10/19/2018 12:32 AM Pierre-Loïc Garoche

Merge branch 'unstable' into lustrec-seal

dae7afb1 09/26/2018 05:00 PM Arnaud Dieumegard

Comments update

02440160 09/26/2018 02:50 PM Arnaud Dieumegard

vhdl and mini_vhdl pp: remove empty lines and useless linebreaks in maps

0cb37f54 09/25/2018 03:55 PM Arnaud Dieumegard

Added missing Open pattern matching case

3b16e10b 09/24/2018 02:15 PM Arnaud Dieumegard

Extraction of signals assignments in component instantiation concurrent statements

08cbfc23 09/24/2018 10:45 AM Arnaud Dieumegard

Added Open vhdl_name_t case in pattern matchings

315cbfda 09/10/2018 04:37 PM Arnaud Dieumegard

Beginning of squeleton for mini_vhdl refactoring

ee7f4a55 08/31/2018 10:56 AM Arnaud Dieumegard

vhdl 2 mini-vhdl code cleaning

9195145a 08/31/2018 10:12 AM Arnaud Dieumegard

First version of implicit memories explicitation

40ac0ede 08/31/2018 10:06 AM Arnaud Dieumegard

Mini vhdl utils simplification

e15a8d65 08/31/2018 10:05 AM Arnaud Dieumegard

Added open in vhdl ast

83e95762 08/31/2018 10:04 AM Arnaud Dieumegard

Vhdl yojson parsing/printing (open)

5cef1e41 08/31/2018 10:04 AM Arnaud Dieumegard

Vhdl pp update (open)

990ae4ee 08/31/2018 10:03 AM Arnaud Dieumegard

Mini vhdl pp update (If, Case, Use clause)

7025c701 08/29/2018 04:57 PM Arnaud Dieumegard

component instantiation generic map resolution

10d196bc 08/29/2018 04:51 PM Arnaud Dieumegard

Bug fix: pp for unary operations

ba9fd1cc 08/29/2018 04:30 PM Arnaud Dieumegard

Resolution of association lists for component instantiation

a16d29bf 08/29/2018 04:29 PM Arnaud Dieumegard

Communalisation of mini-vhdl structure utils

d5b99b54 08/28/2018 03:51 PM Arnaud Dieumegard

Code cleaning in vhdl to mini-vhdl transformation

70ec69a7 08/27/2018 05:37 PM Arnaud Dieumegard

Added missing sensitivity list resolution fold

010428a7 08/27/2018 05:36 PM Arnaud Dieumegard

DB tuple update to contain assigned elements in component

6a2c1a43 08/27/2018 03:07 PM Arnaud Dieumegard

vhdl and mini-vhdl process printing

b6ff3e98 08/27/2018 02:42 PM Arnaud Dieumegard

Removed concurrent assignment statement from mini-vhdl grammar

b2ca2f67 08/27/2018 02:40 PM Arnaud Dieumegard

Mini-vhdl pretty printing for sequential statements and processes

23b37f25 08/27/2018 02:39 PM Arnaud Dieumegard

Concurrent signal assignment statement transformation to concurrent process statement

dcae4909 08/27/2018 02:38 PM Arnaud Dieumegard

Clean ppx deriving comments

3831b5cc 08/24/2018 04:51 PM Arnaud Dieumegard

Update of mini-vhdl pp

4aa05aca 08/24/2018 04:51 PM Arnaud Dieumegard

Building explicit process from concurrent signl assignment

4a92cb37 08/24/2018 01:50 PM Arnaud Dieumegard

Bug fix: resolve entity/arch reference from component instantiation declaration

1732ef44 07/31/2018 02:35 PM Arnaud Dieumegard

Start of the Lustre generator

76f9de64 07/31/2018 11:05 AM Arnaud Dieumegard

mutable object field storing architecture<->entities<->contexts relation, generation of MiniVHDL component instantiation

96cb9cf2 07/31/2018 11:04 AM Arnaud Dieumegard

Added MiniVHDL versions of component instantiation and concurretn statement

9c1ed3ad 07/30/2018 06:26 PM Arnaud Dieumegard

PP order for components and packages

768e8c07 07/30/2018 06:05 PM Arnaud Dieumegard

PP for packages in minivhdl

4a37b02a 07/30/2018 05:33 PM Arnaud Dieumegard

Typo correction

3340aff0 07/30/2018 04:05 PM Arnaud Dieumegard

Some code comments

5bbf7413 07/30/2018 03:59 PM Arnaud Dieumegard

definition of the mini-vhdl types + pp + transformation from vhdl structure

58f8ddf5 07/27/2018 04:23 PM Arnaud Dieumegard

Split PP and Yojson in separate ml for vhdl ast

b0c77300 07/26/2018 06:05 PM Arnaud Dieumegard

PP update: component instantiation type, archi format, port & generic decl in components, signal conditions, return statements expression

1f593d5d 07/26/2018 03:12 PM Arnaud Dieumegard

Printer corrections: signal_condition, conditional_signal, elsif, when conditions, F***ing non-brekaing characters

fc44085e 07/25/2018 04:08 PM Arnaud Dieumegard

PP for procedure call

7f5d0cde 07/25/2018 04:01 PM Arnaud Dieumegard

Qualified expressions, default values for expressions, pp for association_elements

a3f47fb5 07/25/2018 02:26 PM Arnaud Dieumegard

Unbounded array definition printing

d4c98bae 07/25/2018 11:42 AM Arnaud Dieumegard

Use clauses in package definition

d3a35600 07/25/2018 11:29 AM Arnaud Dieumegard

Conditional signals selection, waveform with delay

3d099916 07/24/2018 04:49 PM Arnaud Dieumegard

PP for Subprogram

32614c2d 07/24/2018 03:17 PM Arnaud Dieumegard

Correction of Procedure declaration pp

99ac6a26 07/24/2018 03:16 PM Arnaud Dieumegard

Default value for ProcedureCall assocs

eab3066b 07/24/2018 02:43 PM Arnaud Dieumegard

Aggregate pp, correction of element_assoc pp

7f55f63f 07/24/2018 02:35 PM Arnaud Dieumegard

Default value corrections

ec031ed0 07/24/2018 01:31 PM Arnaud Dieumegard

Added support for declarative items

77bdbec5 07/24/2018 10:53 AM Arnaud Dieumegard

Added support for use clause in architecture declarations

9d5959cb 07/24/2018 10:19 AM Arnaud Dieumegard

Update of component instantiation pp

44998c1e 07/23/2018 05:59 PM Arnaud Dieumegard

Corrections on component instantiation

3b8ba4b5 07/23/2018 04:58 PM Arnaud Dieumegard

Added support for Component declarations in packages

21b75edb 07/23/2018 03:40 PM Arnaud Dieumegard

Pretty printing of assert statements

1f15a1b9 07/23/2018 03:32 PM Arnaud Dieumegard

Constant expression printing with units, Format for case statements, process formatting and name

ab6312e7 07/23/2018 02:54 PM Arnaud Dieumegard

Added support for constants units

248eb65e 07/23/2018 01:54 PM Arnaud Dieumegard

Added support for Array,Record,Enumeration constructs

6d3b5007 07/20/2018 04:52 PM Arnaud Dieumegard

Added support for ProcedureCall statements

6f9095f6 07/19/2018 05:42 PM Arnaud Dieumegard

Update of the component instantiation type to add architecture name reference

27332198 07/19/2018 01:40 PM Arnaud Dieumegard

Added support for component instantiation

389493d3 07/18/2018 11:21 AM Arnaud Dieumegard

code cleaning

d4175560 07/17/2018 04:00 PM Arnaud Dieumegard

Correction of Variables,Signals,Constants definitions of initial values. Now uses an expression.

5f3d7be6 07/17/2018 02:00 PM Arnaud Dieumegard

PP correction for separating spaces

3bc26d43 07/17/2018 01:39 PM Arnaud Dieumegard

PP support for concurrent assignment, processes

52323a31 07/17/2018 10:50 AM Arnaud Dieumegard

PP for Exit, Null and Return statements

00970bbf 07/17/2018 10:42 AM Arnaud Dieumegard

Update of default values for some option constructions + added end if and end case closing of if and case blocks

f779d524 07/16/2018 05:48 PM Arnaud Dieumegard

Update of the vhdl pretty printer

40364f53 07/16/2018 10:44 AM Arnaud Dieumegard

New version of the vhdl import + compilation

83dc064f 07/13/2018 08:05 PM Pierre-Loïc Garoche

Byte/String bug reappeared

f9d0c175 07/13/2018 07:52 PM Pierre-Loïc Garoche

Merge branch 'master' of https://cavale.enseeiht.fr/git/lustrec

2d2144c0 07/13/2018 05:18 PM Pierre-Loïc Garoche

Solved bug#57: issues when indirect init of a pre in horn-traces