| Branch: | Tag: | Revision:

lustrec / src / backends / VHDL @ a16d29bf

# Date Author Comment
a16d29bf 08/29/2018 04:29 PM Arnaud Dieumegard

Communalisation of mini-vhdl structure utils

d5b99b54 08/28/2018 03:51 PM Arnaud Dieumegard

Code cleaning in vhdl to mini-vhdl transformation

70ec69a7 08/27/2018 05:37 PM Arnaud Dieumegard

Added missing sensitivity list resolution fold

010428a7 08/27/2018 05:36 PM Arnaud Dieumegard

DB tuple update to contain assigned elements in component

6a2c1a43 08/27/2018 03:07 PM Arnaud Dieumegard

vhdl and mini-vhdl process printing

b6ff3e98 08/27/2018 02:42 PM Arnaud Dieumegard

Removed concurrent assignment statement from mini-vhdl grammar

b2ca2f67 08/27/2018 02:40 PM Arnaud Dieumegard

Mini-vhdl pretty printing for sequential statements and processes

23b37f25 08/27/2018 02:39 PM Arnaud Dieumegard

Concurrent signal assignment statement transformation to concurrent process statement

dcae4909 08/27/2018 02:38 PM Arnaud Dieumegard

Clean ppx deriving comments

3831b5cc 08/24/2018 04:51 PM Arnaud Dieumegard

Update of mini-vhdl pp

4aa05aca 08/24/2018 04:51 PM Arnaud Dieumegard

Building explicit process from concurrent signl assignment

4a92cb37 08/24/2018 01:50 PM Arnaud Dieumegard

Bug fix: resolve entity/arch reference from component instantiation declaration

1732ef44 07/31/2018 02:35 PM Arnaud Dieumegard

Start of the Lustre generator

76f9de64 07/31/2018 11:05 AM Arnaud Dieumegard

mutable object field storing architecture<->entities<->contexts relation, generation of MiniVHDL component instantiation

96cb9cf2 07/31/2018 11:04 AM Arnaud Dieumegard

Added MiniVHDL versions of component instantiation and concurretn statement

9c1ed3ad 07/30/2018 06:26 PM Arnaud Dieumegard

PP order for components and packages

768e8c07 07/30/2018 06:05 PM Arnaud Dieumegard

PP for packages in minivhdl

4a37b02a 07/30/2018 05:33 PM Arnaud Dieumegard

Typo correction

3340aff0 07/30/2018 04:05 PM Arnaud Dieumegard

Some code comments

5bbf7413 07/30/2018 03:59 PM Arnaud Dieumegard

definition of the mini-vhdl types + pp + transformation from vhdl structure

58f8ddf5 07/27/2018 04:23 PM Arnaud Dieumegard

Split PP and Yojson in separate ml for vhdl ast

b0c77300 07/26/2018 06:05 PM Arnaud Dieumegard

PP update: component instantiation type, archi format, port & generic decl in components, signal conditions, return statements expression

1f593d5d 07/26/2018 03:12 PM Arnaud Dieumegard

Printer corrections: signal_condition, conditional_signal, elsif, when conditions, F***ing non-brekaing characters

fc44085e 07/25/2018 04:08 PM Arnaud Dieumegard

PP for procedure call

7f5d0cde 07/25/2018 04:01 PM Arnaud Dieumegard

Qualified expressions, default values for expressions, pp for association_elements

a3f47fb5 07/25/2018 02:26 PM Arnaud Dieumegard

Unbounded array definition printing

d4c98bae 07/25/2018 11:42 AM Arnaud Dieumegard

Use clauses in package definition

d3a35600 07/25/2018 11:29 AM Arnaud Dieumegard

Conditional signals selection, waveform with delay

3d099916 07/24/2018 04:49 PM Arnaud Dieumegard

PP for Subprogram

32614c2d 07/24/2018 03:17 PM Arnaud Dieumegard

Correction of Procedure declaration pp

99ac6a26 07/24/2018 03:16 PM Arnaud Dieumegard

Default value for ProcedureCall assocs

eab3066b 07/24/2018 02:43 PM Arnaud Dieumegard

Aggregate pp, correction of element_assoc pp

7f55f63f 07/24/2018 02:35 PM Arnaud Dieumegard

Default value corrections

ec031ed0 07/24/2018 01:31 PM Arnaud Dieumegard

Added support for declarative items

77bdbec5 07/24/2018 10:53 AM Arnaud Dieumegard

Added support for use clause in architecture declarations

9d5959cb 07/24/2018 10:19 AM Arnaud Dieumegard

Update of component instantiation pp

44998c1e 07/23/2018 05:59 PM Arnaud Dieumegard

Corrections on component instantiation

3b8ba4b5 07/23/2018 04:58 PM Arnaud Dieumegard

Added support for Component declarations in packages

21b75edb 07/23/2018 03:40 PM Arnaud Dieumegard

Pretty printing of assert statements

1f15a1b9 07/23/2018 03:32 PM Arnaud Dieumegard

Constant expression printing with units, Format for case statements, process formatting and name

ab6312e7 07/23/2018 02:54 PM Arnaud Dieumegard

Added support for constants units

248eb65e 07/23/2018 01:54 PM Arnaud Dieumegard

Added support for Array,Record,Enumeration constructs

6d3b5007 07/20/2018 04:52 PM Arnaud Dieumegard

Added support for ProcedureCall statements

6f9095f6 07/19/2018 05:42 PM Arnaud Dieumegard

Update of the component instantiation type to add architecture name reference

27332198 07/19/2018 01:40 PM Arnaud Dieumegard

Added support for component instantiation

389493d3 07/18/2018 11:21 AM Arnaud Dieumegard

code cleaning

d4175560 07/17/2018 04:00 PM Arnaud Dieumegard

Correction of Variables,Signals,Constants definitions of initial values. Now uses an expression.

5f3d7be6 07/17/2018 02:00 PM Arnaud Dieumegard

PP correction for separating spaces

3bc26d43 07/17/2018 01:39 PM Arnaud Dieumegard

PP support for concurrent assignment, processes

52323a31 07/17/2018 10:50 AM Arnaud Dieumegard

PP for Exit, Null and Return statements

00970bbf 07/17/2018 10:42 AM Arnaud Dieumegard

Update of default values for some option constructions + added end if and end case closing of if and case blocks

f779d524 07/16/2018 05:48 PM Arnaud Dieumegard

Update of the vhdl pretty printer

40364f53 07/16/2018 10:44 AM Arnaud Dieumegard

New version of the vhdl import + compilation

dea84f9e 06/01/2018 05:23 PM Pierre-Loïc Garoche

Working example!

8f9ce6d4 06/01/2018 04:15 PM Pierre-Loïc Garoche

Pom pom pom

5daedd81 06/01/2018 04:14 PM Pierre-Loïc Garoche

Sample value for VHDL

090baab6 06/01/2018 10:02 AM Pierre-Loïc Garoche

Compiling - while doing nothing :)

91cc0f70 06/01/2018 09:32 AM Pierre-Loïc Garoche

Bootstrapping VHDL importer/exporter