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lustrec / src / backends / VHDL / vhdl_ast.ml @ a16d29bf

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# Date Author Comment
dcae4909 08/27/2018 02:38 PM Arnaud Dieumegard

Clean ppx deriving comments

b0c77300 07/26/2018 06:05 PM Arnaud Dieumegard

PP update: component instantiation type, archi format, port & generic decl in components, signal conditions, return statements expression

1f593d5d 07/26/2018 03:12 PM Arnaud Dieumegard

Printer corrections: signal_condition, conditional_signal, elsif, when conditions, F***ing non-brekaing characters

7f5d0cde 07/25/2018 04:01 PM Arnaud Dieumegard

Qualified expressions, default values for expressions, pp for association_elements

d4c98bae 07/25/2018 11:42 AM Arnaud Dieumegard

Use clauses in package definition

d3a35600 07/25/2018 11:29 AM Arnaud Dieumegard

Conditional signals selection, waveform with delay

3d099916 07/24/2018 04:49 PM Arnaud Dieumegard

PP for Subprogram

99ac6a26 07/24/2018 03:16 PM Arnaud Dieumegard

Default value for ProcedureCall assocs

7f55f63f 07/24/2018 02:35 PM Arnaud Dieumegard

Default value corrections

ec031ed0 07/24/2018 01:31 PM Arnaud Dieumegard

Added support for declarative items

77bdbec5 07/24/2018 10:53 AM Arnaud Dieumegard

Added support for use clause in architecture declarations

44998c1e 07/23/2018 05:59 PM Arnaud Dieumegard

Corrections on component instantiation

3b8ba4b5 07/23/2018 04:58 PM Arnaud Dieumegard

Added support for Component declarations in packages

ab6312e7 07/23/2018 02:54 PM Arnaud Dieumegard

Added support for constants units

248eb65e 07/23/2018 01:54 PM Arnaud Dieumegard

Added support for Array,Record,Enumeration constructs

6d3b5007 07/20/2018 04:52 PM Arnaud Dieumegard

Added support for ProcedureCall statements

6f9095f6 07/19/2018 05:42 PM Arnaud Dieumegard

Update of the component instantiation type to add architecture name reference

27332198 07/19/2018 01:40 PM Arnaud Dieumegard

Added support for component instantiation

d4175560 07/17/2018 04:00 PM Arnaud Dieumegard

Correction of Variables,Signals,Constants definitions of initial values. Now uses an expression.

00970bbf 07/17/2018 10:42 AM Arnaud Dieumegard

Update of default values for some option constructions + added end if and end case closing of if and case blocks

40364f53 07/16/2018 10:44 AM Arnaud Dieumegard

New version of the vhdl import + compilation

dea84f9e 06/01/2018 05:23 PM Pierre-Loïc Garoche

Working example!

8f9ce6d4 06/01/2018 04:15 PM Pierre-Loïc Garoche

Pom pom pom

090baab6 06/01/2018 10:02 AM Pierre-Loïc Garoche

Compiling - while doing nothing :)

91cc0f70 06/01/2018 09:32 AM Pierre-Loïc Garoche

Bootstrapping VHDL importer/exporter