Activity
From 07/26/2018 to 08/24/2018
08/24/2018
- 04:52 PM Revision 304640aa (lustrec): update of mini-vhdl to lustre
- 04:51 PM Revision 3831b5cc (lustrec): Update of mini-vhdl pp
- 04:51 PM Revision 4aa05aca (lustrec): Building explicit process from concurrent signl assignment
- 01:50 PM Revision 4a92cb37 (lustrec): Bug fix: resolve entity/arch reference from component instantiation declaration
- 01:49 PM Revision 4a0ba157 (lustrec): Minor comments update
08/04/2018
07/31/2018
- 02:35 PM Revision 1732ef44 (lustrec): Start of the Lustre generator
- 02:34 PM Lustrec-Tests Revision 6ba539c0 (lustrec-tests): Added test laucher for lustre generation
- 11:05 AM Revision 76f9de64 (lustrec): mutable object field storing architecture<->entities<->contexts relation, generation of MiniVHDL component instantiation
- 11:04 AM Revision 96cb9cf2 (lustrec): Added MiniVHDL versions of component instantiation and concurretn statement
07/30/2018
- 06:27 PM Lustrec-Tests Revision 1c688dd0 (lustrec-tests): Continue even if generation fails
- 06:26 PM Revision 9c1ed3ad (lustrec): PP order for components and packages
- 06:07 PM Lustrec-Tests Revision 33a42553 (lustrec-tests): Makefile update for new version of lustrei with command line parameters
- 06:07 PM Lustrec-Tests Revision 928e4486 (lustrec-tests): Test file update for typo
- 06:05 PM Revision 768e8c07 (lustrec): PP for packages in minivhdl
- 06:04 PM Revision b15439da (lustrec): Update of the command line
- 05:33 PM Revision cd7d074b (lustrec): Added command line parameters
- 05:33 PM Revision 4a37b02a (lustrec): Typo correction
- 04:05 PM Revision 3340aff0 (lustrec): Some code comments
- 03:59 PM Revision 5bbf7413 (lustrec): definition of the mini-vhdl types + pp + transformation from vhdl structure
07/27/2018
- 05:46 PM Lustrec-Tests Revision 26dc0008 (lustrec-tests): Added example from some courses
- 04:23 PM Revision 58f8ddf5 (lustrec): Split PP and Yojson in separate ml for vhdl ast
07/26/2018
- 06:12 PM Lustrec-Tests Revision ddabd63e (lustrec-tests): Updated tests for lustrei vhdl import
- 06:05 PM Revision b0c77300 (lustrec): PP update: component instantiation type, archi format, port & generic decl in components, signal conditions, return statements expression
- 03:12 PM Revision 1f593d5d (lustrec): Printer corrections: signal_condition, conditional_signal, elsif, when conditions, F***ing non-brekaing characters
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