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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / EnablePort3_PP.LUSTREC.lus @ cd1faebc

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1 4748b215 hbourbou
-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (ToLustre.m)
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-- Time: 03-Dec-2018 22:34:14
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(*
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Original block name: EnablePort3_PP/case_reset_reset_held
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*)
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node  case_reset_reset_held_39_080_automaton(Cpre_compx_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;);
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var pre_Ccor_x_1 : real;
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	pre_pre_x_1 : real;
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let
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	pre_Ccor_x_1 = 0.000000000000000;
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	pre_pre_x_1 = if (__nb_step > 0) then
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		(pre pre_x_1)
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	    else 0.000000000000000;
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	automaton enabled_case_reset_reset_held_39_080
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	state Active_case_reset_reset_held_39_080:
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	unless (not _isEnabled) restart Inactive_case_reset_reset_held_39_080
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	let
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		(Ccor_x_1, pre_x_1) = case_reset_reset_held_39_080(Cpre_compx_1, __time_step, __nb_step);
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	tel
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	state Inactive_case_reset_reset_held_39_080:
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	unless _isEnabled restart Active_case_reset_reset_held_39_080
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	let
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		Ccor_x_1 = pre_Ccor_x_1;
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		pre_x_1 = pre_pre_x_1;
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	tel
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(*
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Original block name: EnablePort3_PP/case_reset_reset_held
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*)
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node  case_reset_reset_held_39_080(Cpre_compx_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
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	UnitDelay_1 = (0.000000000000000 -> (pre Add_1));
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	Ccor_x_1 = Add_1;
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	pre_x_1 = UnitDelay_1;
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(*
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Original block name: EnablePort3_PP
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*)
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node  EnablePort3_PP(In1_1 : real;
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	Enable_1 : real;)
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returns(Out7_1 : real;
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	pre_Out4_1 : real;);
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var ExecutionCond_of_case_reset_reset_held_39_080 : bool;
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	case_reset_reset_held_1 : real;
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	case_reset_reset_held_2 : real;
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	__time_step : real;
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	__nb_step : int;
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let
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	ExecutionCond_of_case_reset_reset_held_39_080 = (Enable_1 > 0.0);
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	(case_reset_reset_held_1, case_reset_reset_held_2) = case_reset_reset_held_39_080_automaton(In1_1, ExecutionCond_of_case_reset_reset_held_39_080, __time_step, __nb_step);
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	Out7_1 = case_reset_reset_held_1;
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	pre_Out4_1 = case_reset_reset_held_2;
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	__time_step = (0.0 -> ((pre __time_step) + 0.200000000000000));
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	__nb_step = (0 -> ((pre __nb_step) + 1));
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tel