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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / trigger_test_PP.LUSTREC.lus @ b58cc410

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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 20-Mar-2019 11:53:11
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node  real_to_bool(x : real;)
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returns(y : bool;);
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let
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	y = (x <> 0.0);
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem
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*)
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node  TriggeredSubsystem_19_528_condExecSS(In1_1 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;);
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var pre_Out1_1 : bool;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else false;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> TriggeredSubsystem_19_528((In1_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem
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*)
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node  TriggeredSubsystem_19_528(In1_1 : real;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;);
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var LogicalOperator_1 : bool;
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let
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	LogicalOperator_1 = ( real_to_bool(Trigger_1) and real_to_bool(In1_1) );
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	Out1_1 = LogicalOperator_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem1
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*)
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node  TriggeredSubsystem1_27_281_condExecSS(In2_1 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out2_1 : real;);
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var pre_Out2_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out2_1 = (merge _isEnabled_clock 
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		(true -> TriggeredSubsystem1_27_281((In2_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out2_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem1
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*)
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node  TriggeredSubsystem1_27_281(In2_1 : real;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out2_1 : real;);
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var Add_1 : real;
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let
77
	Add_1 = 0.0 + Trigger_1 + In2_1;
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	Out2_1 = Add_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem2
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*)
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node  TriggeredSubsystem2_35_290_condExecSS(In1_1 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> TriggeredSubsystem2_35_290((In1_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem2
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*)
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node  TriggeredSubsystem2_35_290(In1_1 : real;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var Add_1 : real;
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let
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	Add_1 = 0.0 + Trigger_1 + In1_1;
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	Out1_1 = Add_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem3
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*)
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node  TriggeredSubsystem3_43_085_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> TriggeredSubsystem3_43_085((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem3
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*)
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node  TriggeredSubsystem3_43_085(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
143
let
144
	Out1_1 = In1_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem4
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*)
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node  TriggeredSubsystem4_48_103_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
155
var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
158
	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
162
	Out1_1 = (merge _isEnabled_clock 
163
		(true -> TriggeredSubsystem4_48_103((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem4
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*)
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node  TriggeredSubsystem4_48_103(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
173
returns(Out1_1 : real;);
174
let
175
	Out1_1 = In1_1;
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tel
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(*
179
Original block name: trigger_test_PP/TriggeredSubsystem5
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*)
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node  TriggeredSubsystem5_53_287_condExecSS(In1_1 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
187
var pre_Out1_1 : real;
188
	_isEnabled_clock : bool clock;
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let
190
	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
192
	    else 0.0;
193
	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> TriggeredSubsystem5_53_287((In1_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem5
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*)
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node  TriggeredSubsystem5_53_287(In1_1 : real;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
207
var Add_1 : real;
208
let
209
	Add_1 = 0.0 + Trigger_1 + In1_1;
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	Out1_1 = Add_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem6
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*)
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node  TriggeredSubsystem6_61_280_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
220
returns(Out1_1 : real;);
221
var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
229
		(true -> TriggeredSubsystem6_61_280((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem6
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*)
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node  TriggeredSubsystem6_61_280(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
239
returns(Out1_1 : real;);
240
let
241
	Out1_1 = In1_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem7
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*)
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node  TriggeredSubsystem7_66_290_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
253
	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> TriggeredSubsystem7_66_290((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem7
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*)
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node  TriggeredSubsystem7_66_290(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
271
let
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	Out1_1 = In1_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem8
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*)
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node  TriggeredSubsystem8_72_286_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
283
var pre_Out1_1 : real;
284
	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
290
	Out1_1 = (merge _isEnabled_clock 
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		(true -> TriggeredSubsystem8_72_286((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
292
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem8
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*)
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node  TriggeredSubsystem8_72_286(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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let
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	Out1_1 = In1_1;
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem9
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*)
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node  TriggeredSubsystem9_77_062_condExecSS(In1_1 : real;
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	In1_2 : real;
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	In1_3 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
314
	__time_step : real;
315
	__nb_step : int;)
316
returns(Out1_1 : real;
317
	Out1_2 : real;
318
	Out1_3 : real;);
319
var pre_Out1_1 : real;
320
	pre_Out1_2 : real;
321
	pre_Out1_3 : real;
322
	_isEnabled_clock : bool clock;
323
let
324
	pre_Out1_1 = if (__nb_step > 0) then
325
		(pre Out1_1)
326
	    else 0.0;
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	pre_Out1_2 = if (__nb_step > 0) then
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		(pre Out1_2)
329
	    else 0.0;
330
	pre_Out1_3 = if (__nb_step > 0) then
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		(pre Out1_3)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
334
	(Out1_1, Out1_2, Out1_3) = (merge _isEnabled_clock 
335
		(true -> TriggeredSubsystem9_77_062((In1_1 when _isEnabled_clock), (In1_2 when _isEnabled_clock), (In1_3 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
336
		(false -> (pre_Out1_1, pre_Out1_2, pre_Out1_3) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: trigger_test_PP/TriggeredSubsystem9
341
*)
342
node  TriggeredSubsystem9_77_062(In1_1 : real;
343
	In1_2 : real;
344
	In1_3 : real;
345
	Trigger_1 : real;
346
	__time_step : real;
347
	__nb_step : int;)
348
returns(Out1_1 : real;
349
	Out1_2 : real;
350
	Out1_3 : real;);
351
var Add_1 : real;
352
	Add_2 : real;
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	Add_3 : real;
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let
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	Add_1 = 0.0 + Trigger_1 + In1_1;
356
	Add_2 = 0.0 + Trigger_1 + In1_2;
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	Add_3 = 0.0 + Trigger_1 + In1_3;
358
	Out1_1 = Add_1;
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	Out1_2 = Add_2;
360
	Out1_3 = Add_3;
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tel
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(*
364
Original block name: trigger_test_PP
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*)
366
node  trigger_test_PP(In1_1 : real;
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	In2_1 : bool;
368
	In3_1 : real;
369
	In4_1 : int;
370
	In5_1 : real;
371
	In6_1 : real;
372
	In7_1 : real;
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	In7_2 : real;
374
	In7_3 : real;
375
	In8_1 : bool;)
376
returns(Out1_1 : bool;
377
	Out2_1 : real;
378
	Out3_1 : real;
379
	Out4_1 : real;
380
	Out5_1 : real;
381
	Out6_1 : real;
382
	Out7_1 : real;
383
	Out8_1 : real;
384
	Out9_1 : real;
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	Out10_1 : real;
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	Out10_2 : real;
387
	Out10_3 : real;);
388
var ExecutionCond_of_TriggeredSubsystem_19_528 : bool;
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	TriggeredSubsystem_1 : bool;
390
	ExecutionCond_of_TriggeredSubsystem1_27_281 : bool;
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	TriggeredSubsystem1_1 : real;
392
	ExecutionCond_of_TriggeredSubsystem2_35_290 : bool;
393
	TriggeredSubsystem2_1 : real;
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	ExecutionCond_of_TriggeredSubsystem3_43_085 : bool;
395
	TriggeredSubsystem3_1 : real;
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	ExecutionCond_of_TriggeredSubsystem4_48_103 : bool;
397
	TriggeredSubsystem4_1 : real;
398
	ExecutionCond_of_TriggeredSubsystem5_53_287 : bool;
399
	TriggeredSubsystem5_1 : real;
400
	ExecutionCond_of_TriggeredSubsystem6_61_280 : bool;
401
	TriggeredSubsystem6_1 : real;
402
	ExecutionCond_of_TriggeredSubsystem7_66_290 : bool;
403
	TriggeredSubsystem7_1 : real;
404
	ExecutionCond_of_TriggeredSubsystem8_72_286 : bool;
405
	TriggeredSubsystem8_1 : real;
406
	ExecutionCond_of_TriggeredSubsystem9_77_062 : bool;
407
	TriggeredSubsystem9_1 : real;
408
	TriggeredSubsystem9_2 : real;
409
	TriggeredSubsystem9_3 : real;
410
	__time_step : real;
411
	__nb_step : int;
412
let
413
	ExecutionCond_of_TriggeredSubsystem_19_528 = (false -> (In2_1 and (not (pre In2_1))));
414
	TriggeredSubsystem_1 = TriggeredSubsystem_19_528_condExecSS(In1_1, (0.0 -> if ExecutionCond_of_TriggeredSubsystem_19_528 then
415
		1.0
416
	    else 0.0), ExecutionCond_of_TriggeredSubsystem_19_528, __time_step, __nb_step);
417
	ExecutionCond_of_TriggeredSubsystem1_27_281 = (false -> ((not In2_1) and (pre In2_1)));
418
	TriggeredSubsystem1_1 = TriggeredSubsystem1_27_281_condExecSS(In1_1, (0.0 -> if ExecutionCond_of_TriggeredSubsystem1_27_281 then
419
		(- 1.0)
420
	    else 0.0), ExecutionCond_of_TriggeredSubsystem1_27_281, __time_step, __nb_step);
421
	ExecutionCond_of_TriggeredSubsystem2_35_290 = (false -> ((In2_1 and (not (pre In2_1))) or ((not In2_1) and (pre In2_1))));
422
	TriggeredSubsystem2_1 = TriggeredSubsystem2_35_290_condExecSS(In1_1, (0.0 -> if ExecutionCond_of_TriggeredSubsystem2_35_290 then
423
		if (false -> (In2_1 and (not (pre In2_1)))) then
424
		1.0
425
	    else (- 1.0)
426
	    else 0.0), ExecutionCond_of_TriggeredSubsystem2_35_290, __time_step, __nb_step);
427
	ExecutionCond_of_TriggeredSubsystem3_43_085 = (false -> ((In4_1 > 0) and (not (pre (In4_1 > 0)))));
428
	TriggeredSubsystem3_1 = TriggeredSubsystem3_43_085_condExecSS(In3_1, ExecutionCond_of_TriggeredSubsystem3_43_085, __time_step, __nb_step);
429
	ExecutionCond_of_TriggeredSubsystem4_48_103 = (false -> ((not (In4_1 > 0)) and (pre (In4_1 > 0))));
430
	TriggeredSubsystem4_1 = TriggeredSubsystem4_48_103_condExecSS(In3_1, ExecutionCond_of_TriggeredSubsystem4_48_103, __time_step, __nb_step);
431
	ExecutionCond_of_TriggeredSubsystem5_53_287 = (false -> (((In4_1 > 0) and (not (pre (In4_1 > 0)))) or ((not (In4_1 > 0)) and (pre (In4_1 > 0)))));
432
	TriggeredSubsystem5_1 = TriggeredSubsystem5_53_287_condExecSS(In3_1, (0.0 -> if ExecutionCond_of_TriggeredSubsystem5_53_287 then
433
		if (false -> ((In4_1 > 0) and (not (pre (In4_1 > 0))))) then
434
		1.0
435
	    else (- 1.0)
436
	    else 0.0), ExecutionCond_of_TriggeredSubsystem5_53_287, __time_step, __nb_step);
437
	ExecutionCond_of_TriggeredSubsystem6_61_280 = (false -> ((In6_1 > 0.0) and (not (pre (In6_1 > 0.0)))));
438
	TriggeredSubsystem6_1 = TriggeredSubsystem6_61_280_condExecSS(In5_1, ExecutionCond_of_TriggeredSubsystem6_61_280, __time_step, __nb_step);
439
	ExecutionCond_of_TriggeredSubsystem7_66_290 = (false -> ((not (In6_1 > 0.0)) and (pre (In6_1 > 0.0))));
440
	TriggeredSubsystem7_1 = TriggeredSubsystem7_66_290_condExecSS(In5_1, ExecutionCond_of_TriggeredSubsystem7_66_290, __time_step, __nb_step);
441
	ExecutionCond_of_TriggeredSubsystem8_72_286 = (false -> (((In6_1 > 0.0) and (not (pre (In6_1 > 0.0)))) or ((not (In6_1 > 0.0)) and (pre (In6_1 > 0.0)))));
442
	TriggeredSubsystem8_1 = TriggeredSubsystem8_72_286_condExecSS(In5_1, ExecutionCond_of_TriggeredSubsystem8_72_286, __time_step, __nb_step);
443
	ExecutionCond_of_TriggeredSubsystem9_77_062 = (false -> ((In8_1 and (not (pre In8_1))) or ((not In8_1) and (pre In8_1))));
444
	(TriggeredSubsystem9_1, TriggeredSubsystem9_2, TriggeredSubsystem9_3) = TriggeredSubsystem9_77_062_condExecSS(In7_1, In7_2, In7_3, (0.0 -> if ExecutionCond_of_TriggeredSubsystem9_77_062 then
445
		if (false -> (In8_1 and (not (pre In8_1)))) then
446
		1.0
447
	    else (- 1.0)
448
	    else 0.0), ExecutionCond_of_TriggeredSubsystem9_77_062, __time_step, __nb_step);
449
	Out1_1 = TriggeredSubsystem_1;
450
	Out2_1 = TriggeredSubsystem1_1;
451
	Out3_1 = TriggeredSubsystem2_1;
452
	Out4_1 = TriggeredSubsystem3_1;
453
	Out5_1 = TriggeredSubsystem4_1;
454
	Out6_1 = TriggeredSubsystem5_1;
455
	Out7_1 = TriggeredSubsystem6_1;
456
	Out8_1 = TriggeredSubsystem7_1;
457
	Out9_1 = TriggeredSubsystem8_1;
458
	Out10_1 = TriggeredSubsystem9_1;
459
	Out10_2 = TriggeredSubsystem9_2;
460
	Out10_3 = TriggeredSubsystem9_3;
461
	__time_step = (0.0 -> ((pre __time_step) + 1.0));
462
	__nb_step = (0 -> ((pre __nb_step) + 1));
463
tel
464