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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / enable_test_PP.LUSTREC.lus @ b58cc410

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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 19-Mar-2019 21:12:01
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#open <conv>
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node  bool_to_real(x : bool;)
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returns(y : real;);
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let
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	y = if x then
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		1.0
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	    else 0.0;
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tel
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(*
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Original block name: enable_test_PP/EnabledSubsystem
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*)
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node  EnabledSubsystem_11_010_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> EnabledSubsystem_11_010((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: enable_test_PP/EnabledSubsystem
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*)
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node  EnabledSubsystem_11_010(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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let
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	Out1_1 = In1_1;
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tel
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(*
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Original block name: enable_test_PP/EnabledSubsystem1
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*)
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node  EnabledSubsystem1_16_228_condExecSS(In1_1 : real;
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	Enable_1 : bool;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
57
	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> (EnabledSubsystem1_16_228((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
67
Original block name: enable_test_PP/EnabledSubsystem1
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*)
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node  EnabledSubsystem1_16_228(In1_1 : real;
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	Enable_1 : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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let
77
	Add_1 = 0.0 + bool_to_real(Enable_1) + In1_1;
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Out1_1 = UnitDelay_1;
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tel
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(*
83
Original block name: enable_test_PP/EnabledSubsystem2
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*)
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node  EnabledSubsystem2_26_012_condExecSS(In1_1 : real;
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	Enable_1 : int;
87
	Enable_2 : int;
88
	Enable_3 : int;
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	_isEnabled : bool;
90
	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out1_2 : real;
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	Out1_3 : real;);
95
var pre_Out1_1 : real;
96
	pre_Out1_2 : real;
97
	pre_Out1_3 : real;
98
	_isEnabled_clock : bool clock;
99
let
100
	pre_Out1_1 = if (__nb_step > 0) then
101
		(pre Out1_1)
102
	    else 0.0;
103
	pre_Out1_2 = if (__nb_step > 0) then
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		(pre Out1_2)
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	    else 0.0;
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	pre_Out1_3 = if (__nb_step > 0) then
107
		(pre Out1_3)
108
	    else 0.0;
109
	_isEnabled_clock = _isEnabled;
110
	(Out1_1, Out1_2, Out1_3) = (merge _isEnabled_clock 
111
		(true -> (EnabledSubsystem2_26_012((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (Enable_2 when _isEnabled_clock), (Enable_3 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
112
		(false -> (pre_Out1_1, pre_Out1_2, pre_Out1_3) when false(_isEnabled_clock)));
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tel
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(*
116
Original block name: enable_test_PP/EnabledSubsystem2
117
*)
118
node  EnabledSubsystem2_26_012(In1_1 : real;
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	Enable_1 : int;
120
	Enable_2 : int;
121
	Enable_3 : int;
122
	__time_step : real;
123
	__nb_step : int;)
124
returns(Out1_1 : real;
125
	Out1_2 : real;
126
	Out1_3 : real;);
127
var Add_1 : real;
128
	Add_2 : real;
129
	Add_3 : real;
130
	Memory_1 : real;
131
	Memory_2 : real;
132
	Memory_3 : real;
133
let
134
	Add_1 = 0.0 + int_to_real(Enable_1) + In1_1;
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	Add_2 = 0.0 + int_to_real(Enable_2) + In1_1;
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	Add_3 = 0.0 + int_to_real(Enable_3) + In1_1;
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	Memory_1 = (0.0 -> (pre Add_1));
138
	Memory_2 = (0.0 -> (pre Add_2));
139
	Memory_3 = (0.0 -> (pre Add_3));
140
	Out1_1 = Memory_1;
141
	Out1_2 = Memory_2;
142
	Out1_3 = Memory_3;
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tel
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(*
146
Original block name: enable_test_PP/EnabledSubsystem3
147
*)
148
node  EnabledSubsystem3_36_230_condExecSS(In1_1 : real;
149
	Enable_1 : real;
150
	_isEnabled : bool;
151
	__time_step : real;
152
	__nb_step : int;)
153
returns(Out1_1 : real;);
154
var pre_Out1_1 : real;
155
	_isEnabled_clock : bool clock;
156
let
157
	pre_Out1_1 = if (__nb_step > 0) then
158
		(pre Out1_1)
159
	    else 0.0;
160
	_isEnabled_clock = _isEnabled;
161
	Out1_1 = (merge _isEnabled_clock 
162
		(true -> EnabledSubsystem3_36_230((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
163
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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166
(*
167
Original block name: enable_test_PP/EnabledSubsystem3
168
*)
169
node  EnabledSubsystem3_36_230(In1_1 : real;
170
	Enable_1 : real;
171
	__time_step : real;
172
	__nb_step : int;)
173
returns(Out1_1 : real;);
174
var Add_1 : real;
175
let
176
	Add_1 = 0.0 + Enable_1 + In1_1;
177
	Out1_1 = Add_1;
178
tel
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180
(*
181
Original block name: enable_test_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator
182
*)
183
node  Discrete_minus_TimeIntegrator_48_014(f_lpar_x_rpar__1 : real;
184
	__time_step : real;
185
	__nb_step : int;)
186
returns(F_lpar_x_rpar__1 : real;);
187
var Sample_1 : real;
188
	Sum6_1 : real;
189
	UnitDelay_1 : real;
190
let
191
	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
192
	Sum6_1 = 0.0 + Sample_1 + UnitDelay_1;
193
	UnitDelay_1 = (0.0 -> (pre Sum6_1));
194
	F_lpar_x_rpar__1 = UnitDelay_1;
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tel
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197
(*
198
Original block name: enable_test_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator1
199
*)
200
node  Discrete_minus_TimeIntegrator1_60_013(f_lpar_x_rpar__1 : real;
201
	reset_falling_1 : real;
202
	__time_step : real;
203
	__nb_step : int;)
204
returns(F_lpar_x_rpar__1 : real;);
205
var Constant_1 : real;
206
	DataTypeConversion_1 : real;
207
	DataTypeConversion1_1 : real;
208
	Init_1 : real;
209
	Product_1 : real;
210
	Product2_1 : real;
211
	Sample_1 : real;
212
	Sum1_1 : real;
213
	Sum2_1 : real;
214
	Sum3_1 : real;
215
	Sum4_1 : real;
216
	Sum5_1 : real;
217
	Sum6_1 : real;
218
	UnitDelay_1 : real;
219
	UnitDelay1_1 : real;
220
	UnitDelay2_1 : real;
221
	eq0_1 : bool;
222
	ne1_1 : bool;
223
	zero_1 : real;
224
let
225
	Constant_1 = 0.0;
226
	DataTypeConversion_1 = bool_to_real(eq0_1);
227
	DataTypeConversion1_1 = bool_to_real(ne1_1);
228
	Init_1 = 0.0;
229
	Product_1 = 1.0 * Init_1 * UnitDelay1_1;
230
	Product2_1 = 1.0 * Sum3_1 * DataTypeConversion_1 * DataTypeConversion1_1;
231
	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
232
	Sum1_1 = 0.0 + Sample_1 + Sum2_1;
233
	Sum2_1 = 0.0 + Sum4_1 + Product_1;
234
	Sum3_1 = 0.0 - UnitDelay_1 + Init_1;
235
	Sum4_1 = 0.0 + UnitDelay_1 + Product2_1;
236
	Sum5_1 = 0.0 + UnitDelay_1 + Product_1;
237
	Sum6_1 = 0.0 + Sum5_1 + Product2_1;
238
	UnitDelay_1 = (0.0 -> (pre Sum1_1));
239
	UnitDelay1_1 = (1.0 -> (pre Constant_1));
240
	UnitDelay2_1 = (0.0 -> (pre reset_falling_1));
241
	eq0_1 = (reset_falling_1 <= zero_1);
242
	ne1_1 = (UnitDelay2_1 > zero_1);
243
	zero_1 = 0.0;
244
	F_lpar_x_rpar__1 = Sum6_1;
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tel
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(*
248
Original block name: enable_test_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator2
249
*)
250
node  Discrete_minus_TimeIntegrator2_119_012(f_lpar_x_rpar__1 : real;
251
	x0_1 : real;
252
	__time_step : real;
253
	__nb_step : int;)
254
returns(F_lpar_x_rpar__1 : real;);
255
var Constant_1 : real;
256
	Product_1 : real;
257
	Sample_1 : real;
258
	Sum1_1 : real;
259
	Sum2_1 : real;
260
	Sum6_1 : real;
261
	UnitDelay_1 : real;
262
	UnitDelay1_1 : real;
263
let
264
	Constant_1 = 0.0;
265
	Product_1 = 1.0 * x0_1 * UnitDelay1_1;
266
	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
267
	Sum1_1 = 0.0 + Sample_1 + Sum2_1;
268
	Sum2_1 = 0.0 + UnitDelay_1 + Product_1;
269
	Sum6_1 = 0.0 + UnitDelay_1 + Product_1;
270
	UnitDelay_1 = (0.0 -> (pre Sum1_1));
271
	UnitDelay1_1 = (1.0 -> (pre Constant_1));
272
	F_lpar_x_rpar__1 = Sum6_1;
273
tel
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275
(*
276
Original block name: enable_test_PP/EnabledSubsystem4/Discrete_minus_TimeIntegrator3
277
*)
278
node  Discrete_minus_TimeIntegrator3_145_057(f_lpar_x_rpar__1 : real;
279
	reset_level_1 : real;
280
	x0_1 : real;
281
	__time_step : real;
282
	__nb_step : int;)
283
returns(F_lpar_x_rpar__1 : real;);
284
var Add_1 : real;
285
	Constant_1 : real;
286
	DataTypeConversion_1 : real;
287
	DataTypeConversion1_1 : real;
288
	DataTypeConversion2_1 : real;
289
	Product_1 : real;
290
	Product1_1 : real;
291
	Product2_1 : real;
292
	Sample_1 : real;
293
	Sum1_1 : real;
294
	Sum2_1 : real;
295
	Sum3_1 : real;
296
	Sum4_1 : real;
297
	Sum5_1 : real;
298
	Sum6_1 : real;
299
	UnitDelay_1 : real;
300
	UnitDelay1_1 : real;
301
	UnitDelay2_1 : real;
302
	eq0_1 : bool;
303
	ne0_1 : bool;
304
	ne1_1 : bool;
305
	zero_1 : real;
306
let
307
	Add_1 = 0.0 + Product1_1 + Product2_1;
308
	Constant_1 = 0.0;
309
	DataTypeConversion_1 = bool_to_real(ne0_1);
310
	DataTypeConversion1_1 = bool_to_real(eq0_1);
311
	DataTypeConversion2_1 = bool_to_real(ne1_1);
312
	Product_1 = 1.0 * x0_1 * UnitDelay1_1;
313
	Product1_1 = 1.0 * Sum3_1 * DataTypeConversion_1;
314
	Product2_1 = 1.0 * Sum3_1 * DataTypeConversion1_1 * DataTypeConversion2_1;
315
	Sample_1 = (f_lpar_x_rpar__1 * 1.0);
316
	Sum1_1 = 0.0 + Sample_1 + Sum2_1;
317
	Sum2_1 = 0.0 + Sum4_1 + Product_1;
318
	Sum3_1 = 0.0 - UnitDelay_1 + x0_1;
319
	Sum4_1 = 0.0 + UnitDelay_1 + Add_1;
320
	Sum5_1 = 0.0 + UnitDelay_1 + Product_1;
321
	Sum6_1 = 0.0 + Sum5_1 + Add_1;
322
	UnitDelay_1 = (0.0 -> (pre Sum1_1));
323
	UnitDelay1_1 = (1.0 -> (pre Constant_1));
324
	UnitDelay2_1 = (0.0 -> (pre reset_level_1));
325
	eq0_1 = (reset_level_1 = zero_1);
326
	ne0_1 = (reset_level_1 <> zero_1);
327
	ne1_1 = (UnitDelay2_1 <> zero_1);
328
	zero_1 = 0.0;
329
	F_lpar_x_rpar__1 = Sum6_1;
330
tel
331

    
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(*
333
Original block name: enable_test_PP/EnabledSubsystem4
334
*)
335
node  EnabledSubsystem4_44_017_condExecSS(In1_1 : real;
336
	Enable_1 : real;
337
	_isEnabled : bool;
338
	__time_step : real;
339
	__nb_step : int;)
340
returns(Out1_1 : real;
341
	Out2_1 : real;
342
	Out3_1 : real;
343
	Out4_1 : real;);
344
var pre_Out1_1 : real;
345
	pre_Out2_1 : real;
346
	pre_Out3_1 : real;
347
	pre_Out4_1 : real;
348
	_isEnabled_clock : bool clock;
349
let
350
	pre_Out1_1 = if (__nb_step > 0) then
351
		(pre Out1_1)
352
	    else 0.0;
353
	pre_Out2_1 = if (__nb_step > 0) then
354
		(pre Out2_1)
355
	    else 0.0;
356
	pre_Out3_1 = if (__nb_step > 0) then
357
		(pre Out3_1)
358
	    else 0.0;
359
	pre_Out4_1 = if (__nb_step > 0) then
360
		(pre Out4_1)
361
	    else 0.0;
362
	_isEnabled_clock = _isEnabled;
363
	(Out1_1, Out2_1, Out3_1, Out4_1) = (merge _isEnabled_clock 
364
		(true -> (EnabledSubsystem4_44_017((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
365
		(false -> (pre_Out1_1, pre_Out2_1, pre_Out3_1, pre_Out4_1) when false(_isEnabled_clock)));
366
tel
367

    
368
(*
369
Original block name: enable_test_PP/EnabledSubsystem4
370
*)
371
node  EnabledSubsystem4_44_017(In1_1 : real;
372
	Enable_1 : real;
373
	__time_step : real;
374
	__nb_step : int;)
375
returns(Out1_1 : real;
376
	Out2_1 : real;
377
	Out3_1 : real;
378
	Out4_1 : real;);
379
var Add_1 : real;
380
	Discrete_minus_TimeIntegrator_1 : real;
381
	Discrete_minus_TimeIntegrator1_1 : real;
382
	Discrete_minus_TimeIntegrator2_1 : real;
383
	Discrete_minus_TimeIntegrator3_1 : real;
384
let
385
	Add_1 = 0.0 + Enable_1 + In1_1;
386
	Discrete_minus_TimeIntegrator_1 = Discrete_minus_TimeIntegrator_48_014(Add_1, __time_step, __nb_step);
387
	Discrete_minus_TimeIntegrator1_1 = Discrete_minus_TimeIntegrator1_60_013(Add_1, Enable_1, __time_step, __nb_step);
388
	Discrete_minus_TimeIntegrator2_1 = Discrete_minus_TimeIntegrator2_119_012(Add_1, In1_1, __time_step, __nb_step);
389
	Discrete_minus_TimeIntegrator3_1 = Discrete_minus_TimeIntegrator3_145_057(Add_1, Enable_1, In1_1, __time_step, __nb_step);
390
	Out1_1 = Discrete_minus_TimeIntegrator_1;
391
	Out2_1 = Discrete_minus_TimeIntegrator1_1;
392
	Out3_1 = Discrete_minus_TimeIntegrator2_1;
393
	Out4_1 = Discrete_minus_TimeIntegrator3_1;
394
tel
395

    
396
node  EnabledandTriggeredSubsystem_242_010_triggeredSS(In1_1 : real;
397
	_isEnabled : bool;
398
	_isTriggered : bool;
399
	__time_step : real;
400
	__nb_step : int;)
401
returns(Out1_1 : real;);
402
var pre_Out1_1 : real;
403
	_isTriggered_clock : bool clock;
404
let
405
	pre_Out1_1 = if (__nb_step > 0) then
406
		(pre Out1_1)
407
	    else 0.0;
408
	_isTriggered_clock = _isTriggered;
409
	Out1_1 = (merge _isTriggered_clock 
410
		(true -> EnabledandTriggeredSubsystem_242_010((In1_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
411
		(false -> (pre_Out1_1) when false(_isTriggered_clock)));
412
tel
413

    
414
(*
415
Original block name: enable_test_PP/EnabledandTriggeredSubsystem
416
*)
417
node  EnabledandTriggeredSubsystem_242_010_condExecSS(In1_1 : real;
418
	_isEnabled : bool;
419
	_isTriggered : bool;
420
	__time_step : real;
421
	__nb_step : int;)
422
returns(Out1_1 : real;);
423
var pre_Out1_1 : real;
424
	_isEnabled_clock : bool clock;
425
let
426
	pre_Out1_1 = if (__nb_step > 0) then
427
		(pre Out1_1)
428
	    else 0.0;
429
	_isEnabled_clock = _isEnabled;
430
	Out1_1 = (merge _isEnabled_clock 
431
		(true -> EnabledandTriggeredSubsystem_242_010_triggeredSS((In1_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
432
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
433
tel
434

    
435
(*
436
Original block name: enable_test_PP/EnabledandTriggeredSubsystem
437
*)
438
node  EnabledandTriggeredSubsystem_242_010(In1_1 : real;
439
	__time_step : real;
440
	__nb_step : int;)
441
returns(Out1_1 : real;);
442
let
443
	Out1_1 = In1_1;
444
tel
445

    
446
(*
447
Original block name: enable_test_PP/EnabledandTriggeredSubsystem1/Compare
448
To Zero
449
*)
450
node  CompareToZero_253_009(u_1 : real;
451
	__time_step : real;
452
	__nb_step : int;)
453
returns(y_1 : bool;);
454
var Compare_1 : bool;
455
	Constant_1 : real;
456
let
457
	Compare_1 = (u_1 <= Constant_1);
458
	Constant_1 = 0.0;
459
	y_1 = Compare_1;
460
tel
461

    
462
node  EnabledandTriggeredSubsystem1_248_010_triggeredSS(In1_1 : real;
463
	Enable_1 : bool;
464
	Trigger_1 : real;
465
	_isEnabled : bool;
466
	_isTriggered : bool;
467
	__time_step : real;
468
	__nb_step : int;)
469
returns(Out1_1 : bool;);
470
var pre_Out1_1 : bool;
471
	_isTriggered_clock : bool clock;
472
let
473
	pre_Out1_1 = if (__nb_step > 0) then
474
		(pre Out1_1)
475
	    else false;
476
	_isTriggered_clock = _isTriggered;
477
	Out1_1 = (merge _isTriggered_clock 
478
		(true -> EnabledandTriggeredSubsystem1_248_010((In1_1 when _isTriggered_clock), (Enable_1 when _isTriggered_clock), (Trigger_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
479
		(false -> (pre_Out1_1) when false(_isTriggered_clock)));
480
tel
481

    
482
(*
483
Original block name: enable_test_PP/EnabledandTriggeredSubsystem1
484
*)
485
node  EnabledandTriggeredSubsystem1_248_010_condExecSS(In1_1 : real;
486
	Enable_1 : bool;
487
	Trigger_1 : real;
488
	_isEnabled : bool;
489
	_isTriggered : bool;
490
	__time_step : real;
491
	__nb_step : int;)
492
returns(Out1_1 : bool;);
493
var pre_Out1_1 : bool;
494
	_isEnabled_clock : bool clock;
495
let
496
	pre_Out1_1 = if (__nb_step > 0) then
497
		(pre Out1_1)
498
	    else false;
499
	_isEnabled_clock = _isEnabled;
500
	Out1_1 = (merge _isEnabled_clock 
501
		(true -> EnabledandTriggeredSubsystem1_248_010_triggeredSS((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
502
		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
503
tel
504

    
505
(*
506
Original block name: enable_test_PP/EnabledandTriggeredSubsystem1
507
*)
508
node  EnabledandTriggeredSubsystem1_248_010(In1_1 : real;
509
	Enable_1 : bool;
510
	Trigger_1 : real;
511
	__time_step : real;
512
	__nb_step : int;)
513
returns(Out1_1 : bool;);
514
var Add_1 : real;
515
	CompareToZero_1 : bool;
516
	LogicalOperator_1 : bool;
517
let
518
	Add_1 = 0.0 + Trigger_1 + In1_1;
519
	CompareToZero_1 = CompareToZero_253_009(Add_1, __time_step, __nb_step);
520
	LogicalOperator_1 = ( CompareToZero_1 and Enable_1 );
521
	Out1_1 = LogicalOperator_1;
522
tel
523

    
524
(*
525
Original block name: enable_test_PP
526
*)
527
node  enable_test_PP(In1_1 : real;
528
	In2_1 : bool;
529
	In3_1 : int;
530
	In3_2 : int;
531
	In3_3 : int;
532
	In4_1 : real;
533
	In5_1 : real;
534
	In6_1 : real;)
535
returns(Out3_1 : real;
536
	Out1_1 : real;
537
	Out2_1 : real;
538
	Out4_1 : real;
539
	Out4_2 : real;
540
	Out4_3 : real;
541
	Out5_1 : real;
542
	Out6_1 : bool;
543
	Out7_1 : real;
544
	Out8_1 : real;
545
	Out9_1 : real;
546
	Out10_1 : real;);
547
var ExecutionCond_of_EnabledSubsystem_11_010 : bool;
548
	EnabledSubsystem_1 : real;
549
	ExecutionCond_of_EnabledSubsystem1_16_228 : bool;
550
	EnabledSubsystem1_1 : real;
551
	ExecutionCond_of_EnabledSubsystem2_26_012 : bool;
552
	EnabledSubsystem2_1 : real;
553
	EnabledSubsystem2_2 : real;
554
	EnabledSubsystem2_3 : real;
555
	ExecutionCond_of_EnabledSubsystem3_36_230 : bool;
556
	EnabledSubsystem3_1 : real;
557
	ExecutionCond_of_EnabledSubsystem4_44_017 : bool;
558
	EnabledSubsystem4_1 : real;
559
	EnabledSubsystem4_2 : real;
560
	EnabledSubsystem4_3 : real;
561
	EnabledSubsystem4_4 : real;
562
	ExecutionCond_of_EnabledandTriggeredSubsystem_242_010 : bool;
563
	TriggerCond_of_EnabledandTriggeredSubsystem_242_010 : bool;
564
	EnableCond_of_EnabledandTriggeredSubsystem_242_010 : bool;
565
	EnabledandTriggeredSubsystem_1 : real;
566
	ExecutionCond_of_EnabledandTriggeredSubsystem1_248_010 : bool;
567
	TriggerCond_of_EnabledandTriggeredSubsystem1_248_010 : bool;
568
	EnableCond_of_EnabledandTriggeredSubsystem1_248_010 : bool;
569
	EnabledandTriggeredSubsystem1_1 : bool;
570
	__time_step : real;
571
	__nb_step : int;
572
let
573
	ExecutionCond_of_EnabledSubsystem_11_010 = In2_1;
574
	EnabledSubsystem_1 = EnabledSubsystem_11_010_condExecSS(In1_1, ExecutionCond_of_EnabledSubsystem_11_010, __time_step, __nb_step);
575
	ExecutionCond_of_EnabledSubsystem1_16_228 = In2_1;
576
	EnabledSubsystem1_1 = EnabledSubsystem1_16_228_condExecSS(In1_1, In2_1, ExecutionCond_of_EnabledSubsystem1_16_228, __time_step, __nb_step);
577
	ExecutionCond_of_EnabledSubsystem2_26_012 = ( (In3_1 > 0) or (In3_2 > 0) or (In3_3 > 0) );
578
	(EnabledSubsystem2_1, EnabledSubsystem2_2, EnabledSubsystem2_3) = EnabledSubsystem2_26_012_condExecSS(In1_1, In3_1, In3_2, In3_3, ExecutionCond_of_EnabledSubsystem2_26_012, __time_step, __nb_step);
579
	ExecutionCond_of_EnabledSubsystem3_36_230 = (In4_1 > 0.0);
580
	EnabledSubsystem3_1 = EnabledSubsystem3_36_230_condExecSS(In1_1, In4_1, ExecutionCond_of_EnabledSubsystem3_36_230, __time_step, __nb_step);
581
	ExecutionCond_of_EnabledSubsystem4_44_017 = (In6_1 > 0.0);
582
	(EnabledSubsystem4_1, EnabledSubsystem4_2, EnabledSubsystem4_3, EnabledSubsystem4_4) = EnabledSubsystem4_44_017_condExecSS(In1_1, In6_1, ExecutionCond_of_EnabledSubsystem4_44_017, __time_step, __nb_step);
583
	EnableCond_of_EnabledandTriggeredSubsystem_242_010 = In2_1;
584
	TriggerCond_of_EnabledandTriggeredSubsystem_242_010 = (false -> (In2_1 and (not (pre In2_1))));
585
	ExecutionCond_of_EnabledandTriggeredSubsystem_242_010 = (EnableCond_of_EnabledandTriggeredSubsystem_242_010 and TriggerCond_of_EnabledandTriggeredSubsystem_242_010);
586
	EnabledandTriggeredSubsystem_1 = EnabledandTriggeredSubsystem_242_010_condExecSS(In1_1, EnableCond_of_EnabledandTriggeredSubsystem_242_010, TriggerCond_of_EnabledandTriggeredSubsystem_242_010, __time_step, __nb_step);
587
	EnableCond_of_EnabledandTriggeredSubsystem1_248_010 = In2_1;
588
	TriggerCond_of_EnabledandTriggeredSubsystem1_248_010 = (false -> ((not In2_1) and (pre In2_1)));
589
	ExecutionCond_of_EnabledandTriggeredSubsystem1_248_010 = (EnableCond_of_EnabledandTriggeredSubsystem1_248_010 and TriggerCond_of_EnabledandTriggeredSubsystem1_248_010);
590
	EnabledandTriggeredSubsystem1_1 = EnabledandTriggeredSubsystem1_248_010_condExecSS(In5_1, In2_1, (0.0 -> if TriggerCond_of_EnabledandTriggeredSubsystem1_248_010 then
591
		(- 1.0)
592
	    else 0.0), EnableCond_of_EnabledandTriggeredSubsystem1_248_010, TriggerCond_of_EnabledandTriggeredSubsystem1_248_010, __time_step, __nb_step);
593
	Out3_1 = EnabledSubsystem_1;
594
	Out1_1 = EnabledandTriggeredSubsystem_1;
595
	Out2_1 = EnabledSubsystem1_1;
596
	Out4_1 = EnabledSubsystem2_1;
597
	Out4_2 = EnabledSubsystem2_2;
598
	Out4_3 = EnabledSubsystem2_3;
599
	Out5_1 = EnabledSubsystem3_1;
600
	Out6_1 = EnabledandTriggeredSubsystem1_1;
601
	Out7_1 = EnabledSubsystem4_1;
602
	Out8_1 = EnabledSubsystem4_2;
603
	Out9_1 = EnabledSubsystem4_3;
604
	Out10_1 = EnabledSubsystem4_4;
605
	__time_step = (0.0 -> ((pre __time_step) + 1.0));
606
	__nb_step = (0 -> ((pre __nb_step) + 1));
607
tel
608