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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / enable_test2_PP.LUSTREC.lus @ b58cc410

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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 20-Mar-2019 13:44:19
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node  Subsystem0_19_615_triggeredSS(In1_1 : real;
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	_isEnabled : bool;
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	_isTriggered : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isTriggered_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isTriggered_clock = _isTriggered;
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	Out1_1 = (merge _isTriggered_clock 
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		(true -> Subsystem0_19_615((In1_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
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		(false -> (pre_Out1_1) when false(_isTriggered_clock)));
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tel
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(*
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Original block name: enable_test2_PP/Subsystem0
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*)
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node  Subsystem0_19_615_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	_isTriggered : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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var pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	Out1_1 = (merge _isEnabled_clock 
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		(true -> Subsystem0_19_615_triggeredSS((In1_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: enable_test2_PP/Subsystem0
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*)
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node  Subsystem0_19_615(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;);
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let
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	Out1_1 = In1_1;
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tel
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(*
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Original block name: enable_test2_PP/Subsystem1/Compare
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To Zero
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*)
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node  CompareToZero_54_666(u_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(y_1 : bool;);
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var Compare_1 : bool;
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	Constant_1 : real;
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let
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	Compare_1 = (u_1 <= Constant_1);
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	Constant_1 = 0.0;
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	y_1 = Compare_1;
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tel
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node  Subsystem1_40_723_triggeredSS(In1_1 : real;
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	Enable_1 : bool;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	_isTriggered : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;
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	Out2_1 : real;);
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var pre_Out1_1 : bool;
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	pre_Out2_1 : real;
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	_isTriggered_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else false;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	_isTriggered_clock = _isTriggered;
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	(Out1_1, Out2_1) = (merge _isTriggered_clock 
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		(true -> Subsystem1_40_723((In1_1 when _isTriggered_clock), (Enable_1 when _isTriggered_clock), (Trigger_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
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		(false -> (pre_Out1_1, pre_Out2_1) when false(_isTriggered_clock)));
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tel
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(*
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Original block name: enable_test2_PP/Subsystem1
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*)
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node  Subsystem1_40_723_condExecSS(In1_1 : real;
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	Enable_1 : bool;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	_isTriggered : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;
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	Out2_1 : real;);
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var pre_Out1_1 : bool;
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	pre_Out2_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else false;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Out1_1, Out2_1) = (merge _isEnabled_clock 
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		(true -> Subsystem1_40_723_triggeredSS((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: enable_test2_PP/Subsystem1
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*)
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node  Subsystem1_40_723(In1_1 : real;
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	Enable_1 : bool;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;
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	Out2_1 : real;);
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var Add_1 : real;
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	CompareToZero_1 : bool;
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	LogicalOperator_1 : bool;
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let
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	Add_1 = 0.0 + Trigger_1 + In1_1;
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	CompareToZero_1 = CompareToZero_54_666(Add_1, __time_step, __nb_step);
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	LogicalOperator_1 = ( CompareToZero_1 and Enable_1 );
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	Out1_1 = LogicalOperator_1;
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	Out2_1 = Add_1;
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tel
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(*
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Original block name: enable_test2_PP/Subsystem2/Compare
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To Zero
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*)
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node  CompareToZero_88_362(u_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(y_1 : bool;);
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var Compare_1 : bool;
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	Constant_1 : real;
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let
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	Compare_1 = (u_1 <= Constant_1);
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	Constant_1 = 0.0;
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	y_1 = Compare_1;
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tel
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node  Subsystem2_83_387_triggeredSS(In1_1 : real;
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	Enable_1 : bool;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	_isTriggered : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;
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	Out2_1 : real;);
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var pre_Out1_1 : bool;
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	pre_Out2_1 : real;
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	_isTriggered_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else false;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	_isTriggered_clock = _isTriggered;
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	(Out1_1, Out2_1) = (merge _isTriggered_clock 
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		(true -> Subsystem2_83_387((In1_1 when _isTriggered_clock), (Enable_1 when _isTriggered_clock), (Trigger_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
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		(false -> (pre_Out1_1, pre_Out2_1) when false(_isTriggered_clock)));
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tel
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(*
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Original block name: enable_test2_PP/Subsystem2
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*)
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node  Subsystem2_83_387_condExecSS(In1_1 : real;
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	Enable_1 : bool;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	_isTriggered : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;
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	Out2_1 : real;);
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var pre_Out1_1 : bool;
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	pre_Out2_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else false;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Out1_1, Out2_1) = (merge _isEnabled_clock 
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		(true -> (Subsystem2_83_387_triggeredSS((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
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		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: enable_test2_PP/Subsystem2
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*)
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node  Subsystem2_83_387(In1_1 : real;
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	Enable_1 : bool;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : bool;
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	Out2_1 : real;);
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var Add_1 : real;
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	CompareToZero_1 : bool;
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	LogicalOperator_1 : bool;
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let
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	Add_1 = 0.0 + Trigger_1 + In1_1;
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	CompareToZero_1 = CompareToZero_88_362(Add_1, __time_step, __nb_step);
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	LogicalOperator_1 = ( CompareToZero_1 and Enable_1 );
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	Out1_1 = LogicalOperator_1;
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	Out2_1 = Add_1;
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tel
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(*
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Original block name: enable_test2_PP
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*)
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node  enable_test2_PP(in1_1 : real;
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	in2_1 : real;
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	in3_1 : bool;)
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returns(Out1_1 : real;
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	Out2_1 : bool;
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	Out3_1 : real;
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	Out4_1 : bool;
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	Out5_1 : real;);
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var ExecutionCond_of_Subsystem0_19_615 : bool;
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	TriggerCond_of_Subsystem0_19_615 : bool;
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	EnableCond_of_Subsystem0_19_615 : bool;
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	Subsystem0_1 : real;
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	ExecutionCond_of_Subsystem1_40_723 : bool;
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	TriggerCond_of_Subsystem1_40_723 : bool;
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	EnableCond_of_Subsystem1_40_723 : bool;
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	Subsystem1_1 : bool;
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	Subsystem1_2 : real;
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	ExecutionCond_of_Subsystem2_83_387 : bool;
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	TriggerCond_of_Subsystem2_83_387 : bool;
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	EnableCond_of_Subsystem2_83_387 : bool;
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	Subsystem2_1 : bool;
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	Subsystem2_2 : real;
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	__time_step : real;
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	__nb_step : int;
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let
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	EnableCond_of_Subsystem0_19_615 = in3_1;
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	TriggerCond_of_Subsystem0_19_615 = (false -> ((not in3_1) and (pre in3_1)));
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	ExecutionCond_of_Subsystem0_19_615 = (EnableCond_of_Subsystem0_19_615 and TriggerCond_of_Subsystem0_19_615);
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	Subsystem0_1 = Subsystem0_19_615_condExecSS(in2_1, EnableCond_of_Subsystem0_19_615, TriggerCond_of_Subsystem0_19_615, __time_step, __nb_step);
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	EnableCond_of_Subsystem1_40_723 = in3_1;
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	TriggerCond_of_Subsystem1_40_723 = (false -> ((in3_1 and (not (pre in3_1))) or ((not in3_1) and (pre in3_1))));
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	ExecutionCond_of_Subsystem1_40_723 = (EnableCond_of_Subsystem1_40_723 and TriggerCond_of_Subsystem1_40_723);
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	(Subsystem1_1, Subsystem1_2) = Subsystem1_40_723_condExecSS(in1_1, in3_1, (0.0 -> if TriggerCond_of_Subsystem1_40_723 then
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		if (false -> (in3_1 and (not (pre in3_1)))) then
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		1.0
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	    else (- 1.0)
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	    else 0.0), EnableCond_of_Subsystem1_40_723, TriggerCond_of_Subsystem1_40_723, __time_step, __nb_step);
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	EnableCond_of_Subsystem2_83_387 = in3_1;
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	TriggerCond_of_Subsystem2_83_387 = (false -> ((in3_1 and (not (pre in3_1))) or ((not in3_1) and (pre in3_1))));
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	ExecutionCond_of_Subsystem2_83_387 = (EnableCond_of_Subsystem2_83_387 and TriggerCond_of_Subsystem2_83_387);
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	(Subsystem2_1, Subsystem2_2) = Subsystem2_83_387_condExecSS(in1_1, in3_1, (0.0 -> if TriggerCond_of_Subsystem2_83_387 then
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		if (false -> (in3_1 and (not (pre in3_1)))) then
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		1.0
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	    else (- 1.0)
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	    else 0.0), EnableCond_of_Subsystem2_83_387, TriggerCond_of_Subsystem2_83_387, __time_step, __nb_step);
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	Out1_1 = Subsystem0_1;
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	Out2_1 = Subsystem1_1;
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	Out3_1 = Subsystem1_2;
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	Out4_1 = Subsystem2_1;
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	Out5_1 = Subsystem2_2;
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	__time_step = (0.0 -> ((pre __time_step) + 0.20));
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	__nb_step = (0 -> ((pre __nb_step) + 1));
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tel
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