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lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / Triggered_Subsystem_PP.LUSTREC.lus @ b58cc410

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-- This file has been generated by CoCoSim2.
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-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
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-- Time: 12-Mar-2019 22:09:16
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(*
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Original block name: Triggered_Subsystem_PP/Triggered_Counter/Subsystem
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*)
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node  Subsystem_179_096_condExecSS(In1_1 : real;
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	Enable_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;);
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var pre_Out1_1 : real;
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	pre_Out2_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Out1_1, Out2_1) = (merge _isEnabled_clock 
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		(true -> (Subsystem_179_096((In1_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock)) every (false -> (_isEnabled_clock and (not (pre _isEnabled_clock)))))) 
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		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: Triggered_Subsystem_PP/Triggered_Counter/Subsystem
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*)
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node  Subsystem_179_096(In1_1 : real;
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	Enable_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + In1_1 + UnitDelay_1;
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Out1_1 = Add_1;
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	Out2_1 = Enable_1;
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tel
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(*
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Original block name: Triggered_Subsystem_PP/Triggered_Counter
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*)
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node  Triggered_Counter_174_083_condExecSS(In1_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;);
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var pre_Out1_1 : real;
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	pre_Out2_1 : real;
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	pre_Out3_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	pre_Out2_1 = if (__nb_step > 0) then
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		(pre Out2_1)
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	    else 0.0;
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	pre_Out3_1 = if (__nb_step > 0) then
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		(pre Out3_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Out1_1, Out2_1, Out3_1) = (merge _isEnabled_clock 
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		(true -> Triggered_Counter_174_083((In1_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Out1_1, pre_Out2_1, pre_Out3_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: Triggered_Subsystem_PP/Triggered_Counter
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*)
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node  Triggered_Counter_174_083(In1_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;);
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var Add_1 : real;
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	ExecutionCond_of_Subsystem_179_096 : bool;
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	Subsystem_1 : real;
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	Subsystem_2 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + In1_1 + UnitDelay_1;
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	ExecutionCond_of_Subsystem_179_096 = (In1_1 > 0.0);
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	(Subsystem_1, Subsystem_2) = Subsystem_179_096_condExecSS(In1_1, In1_1, ExecutionCond_of_Subsystem_179_096, __time_step, __nb_step);
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Out1_1 = Add_1;
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	Out2_1 = Subsystem_1;
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	Out3_1 = Subsystem_2;
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tel
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(*
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Original block name: Triggered_Subsystem_PP/case_either
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*)
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node  case_either_214_085_condExecSS(Cpre_compx_1 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var pre_Ccor_x_1 : real;
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	pre_pre_x_1 : real;
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	pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Ccor_x_1 = if (__nb_step > 0) then
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		(pre Ccor_x_1)
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	    else 0.0;
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	pre_pre_x_1 = if (__nb_step > 0) then
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		(pre pre_x_1)
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	    else 0.0;
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Ccor_x_1, pre_x_1, Out1_1) = (merge _isEnabled_clock 
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		(true -> case_either_214_085((Cpre_compx_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Ccor_x_1, pre_pre_x_1, pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: Triggered_Subsystem_PP/case_either
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*)
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node  case_either_214_085(Cpre_compx_1 : real;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Ccor_x_1 = Add_1;
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	pre_x_1 = UnitDelay_1;
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	Out1_1 = Trigger_1;
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tel
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(*
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Original block name: Triggered_Subsystem_PP/case_falling
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*)
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node  case_falling_230_305_condExecSS(Cpre_compx_1 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var pre_Ccor_x_1 : real;
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	pre_pre_x_1 : real;
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	pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Ccor_x_1 = if (__nb_step > 0) then
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		(pre Ccor_x_1)
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	    else 0.0;
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	pre_pre_x_1 = if (__nb_step > 0) then
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		(pre pre_x_1)
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	    else 0.0;
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Ccor_x_1, pre_x_1, Out1_1) = (merge _isEnabled_clock 
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		(true -> case_falling_230_305((Cpre_compx_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Ccor_x_1, pre_pre_x_1, pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: Triggered_Subsystem_PP/case_falling
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*)
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node  case_falling_230_305(Cpre_compx_1 : real;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Ccor_x_1 = Add_1;
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	pre_x_1 = UnitDelay_1;
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	Out1_1 = Trigger_1;
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tel
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(*
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Original block name: Triggered_Subsystem_PP/case_rising
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*)
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node  case_rising_246_097_condExecSS(Cpre_compx_1 : real;
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	Trigger_1 : real;
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	_isEnabled : bool;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var pre_Ccor_x_1 : real;
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	pre_pre_x_1 : real;
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	pre_Out1_1 : real;
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	_isEnabled_clock : bool clock;
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let
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	pre_Ccor_x_1 = if (__nb_step > 0) then
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		(pre Ccor_x_1)
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	    else 0.0;
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	pre_pre_x_1 = if (__nb_step > 0) then
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		(pre pre_x_1)
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	    else 0.0;
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	pre_Out1_1 = if (__nb_step > 0) then
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		(pre Out1_1)
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	    else 0.0;
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	_isEnabled_clock = _isEnabled;
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	(Ccor_x_1, pre_x_1, Out1_1) = (merge _isEnabled_clock 
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		(true -> case_rising_246_097((Cpre_compx_1 when _isEnabled_clock), (Trigger_1 when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
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		(false -> (pre_Ccor_x_1, pre_pre_x_1, pre_Out1_1) when false(_isEnabled_clock)));
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tel
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(*
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Original block name: Triggered_Subsystem_PP/case_rising
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*)
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node  case_rising_246_097(Cpre_compx_1 : real;
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	Trigger_1 : real;
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	__time_step : real;
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	__nb_step : int;)
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returns(Ccor_x_1 : real;
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	pre_x_1 : real;
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	Out1_1 : real;);
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var Add_1 : real;
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	UnitDelay_1 : real;
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let
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	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
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	UnitDelay_1 = (0.0 -> (pre Add_1));
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	Ccor_x_1 = Add_1;
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	pre_x_1 = UnitDelay_1;
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	Out1_1 = Trigger_1;
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tel
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(*
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Original block name: Triggered_Subsystem_PP
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*)
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node  Triggered_Subsystem_PP(In1_1 : real;
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	Enable_1 : real;)
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returns(Out1_1 : real;
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	Out2_1 : real;
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	Out3_1 : real;
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	Out4_1 : real;
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	Out5_1 : real;
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	Out6_1 : real;
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	pre_Out1_1 : real;
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	pre_Out2_1 : real;
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	pre_Out3_1 : real;
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	Out8_1 : real;
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	Out7_1 : real;
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	Out9_1 : real;);
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var ExecutionCond_of_Triggered_Counter_174_083 : bool;
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	Triggered_Counter_1 : real;
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	Triggered_Counter_2 : real;
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	Triggered_Counter_3 : real;
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	ExecutionCond_of_case_either_214_085 : bool;
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	case_either_1 : real;
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	case_either_2 : real;
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	case_either_3 : real;
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	ExecutionCond_of_case_falling_230_305 : bool;
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	case_falling_1 : real;
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	case_falling_2 : real;
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	case_falling_3 : real;
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	ExecutionCond_of_case_rising_246_097 : bool;
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	case_rising_1 : real;
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	case_rising_2 : real;
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	case_rising_3 : real;
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	__time_step : real;
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	__nb_step : int;
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let
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	ExecutionCond_of_Triggered_Counter_174_083 = (false -> ((Enable_1 > 0.0) and (not (pre (Enable_1 > 0.0)))));
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	(Triggered_Counter_1, Triggered_Counter_2, Triggered_Counter_3) = Triggered_Counter_174_083_condExecSS(In1_1, ExecutionCond_of_Triggered_Counter_174_083, __time_step, __nb_step);
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	ExecutionCond_of_case_either_214_085 = (false -> (((Enable_1 > 0.0) and (not (pre (Enable_1 > 0.0)))) or ((not (Enable_1 > 0.0)) and (pre (Enable_1 > 0.0)))));
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	(case_either_1, case_either_2, case_either_3) = case_either_214_085_condExecSS(In1_1, (0.0 -> if ExecutionCond_of_case_either_214_085 then
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		if (false -> ((Enable_1 > 0.0) and (not (pre (Enable_1 > 0.0))))) then
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		1.0
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	    else (- 1.0)
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	    else 0.0), ExecutionCond_of_case_either_214_085, __time_step, __nb_step);
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	ExecutionCond_of_case_falling_230_305 = (false -> ((not (Enable_1 > 0.0)) and (pre (Enable_1 > 0.0))));
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	(case_falling_1, case_falling_2, case_falling_3) = case_falling_230_305_condExecSS(In1_1, (0.0 -> if ExecutionCond_of_case_falling_230_305 then
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		(- 1.0)
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	    else 0.0), ExecutionCond_of_case_falling_230_305, __time_step, __nb_step);
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	ExecutionCond_of_case_rising_246_097 = (false -> ((Enable_1 > 0.0) and (not (pre (Enable_1 > 0.0)))));
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	(case_rising_1, case_rising_2, case_rising_3) = case_rising_246_097_condExecSS(In1_1, (0.0 -> if ExecutionCond_of_case_rising_246_097 then
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		1.0
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	    else 0.0), ExecutionCond_of_case_rising_246_097, __time_step, __nb_step);
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	Out1_1 = Triggered_Counter_1;
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	Out2_1 = Triggered_Counter_2;
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	Out3_1 = Triggered_Counter_3;
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	Out4_1 = case_rising_1;
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	Out5_1 = case_falling_1;
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	Out6_1 = case_either_1;
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	pre_Out1_1 = case_rising_2;
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	pre_Out2_1 = case_falling_2;
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	pre_Out3_1 = case_either_2;
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	Out8_1 = case_rising_3;
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	Out7_1 = case_falling_3;
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	Out9_1 = case_either_3;
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	__time_step = (0.0 -> ((pre __time_step) + 0.20));
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	__nb_step = (0 -> ((pre __nb_step) + 1));
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tel
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