Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / regression_tests / lustre_files / success / Simulink / src_many_files / TriggeredEnabled_Subsystem_PP.LUSTREC.lus @ b58cc410

History | View | Annotate | Download (6.33 KB)

1
-- This file has been generated by CoCoSim2.
2

    
3
-- Compiler: Lustre compiler 2 (nasa_toLustre.ToLustre.m)
4
-- Time: 12-Mar-2019 22:08:52
5
node  Enabled_Counter_99_939_triggeredSS(In1_1 : real;
6
	_isEnabled : bool;
7
	_isTriggered : bool;
8
	__time_step : real;
9
	__nb_step : int;)
10
returns(Out1_1 : real;
11
	Out2_1 : real;);
12
var pre_Out1_1 : real;
13
	pre_Out2_1 : real;
14
	_isTriggered_clock : bool clock;
15
let
16
	pre_Out1_1 = if (__nb_step > 0) then
17
		(pre Out1_1)
18
	    else 0.0;
19
	pre_Out2_1 = if (__nb_step > 0) then
20
		(pre Out2_1)
21
	    else 0.0;
22
	_isTriggered_clock = _isTriggered;
23
	(Out1_1, Out2_1) = (merge _isTriggered_clock 
24
		(true -> Enabled_Counter_99_939((In1_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
25
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isTriggered_clock)));
26
tel
27

    
28
(*
29
Original block name: TriggeredEnabled_Subsystem_PP/Enabled_Counter
30
*)
31
node  Enabled_Counter_99_939_condExecSS(In1_1 : real;
32
	_isEnabled : bool;
33
	_isTriggered : bool;
34
	__time_step : real;
35
	__nb_step : int;)
36
returns(Out1_1 : real;
37
	Out2_1 : real;);
38
var pre_Out1_1 : real;
39
	pre_Out2_1 : real;
40
	_isEnabled_clock : bool clock;
41
let
42
	pre_Out1_1 = if (__nb_step > 0) then
43
		(pre Out1_1)
44
	    else 0.0;
45
	pre_Out2_1 = if (__nb_step > 0) then
46
		(pre Out2_1)
47
	    else 0.0;
48
	_isEnabled_clock = _isEnabled;
49
	(Out1_1, Out2_1) = (merge _isEnabled_clock 
50
		(true -> Enabled_Counter_99_939_triggeredSS((In1_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
51
		(false -> (pre_Out1_1, pre_Out2_1) when false(_isEnabled_clock)));
52
tel
53

    
54
(*
55
Original block name: TriggeredEnabled_Subsystem_PP/Enabled_Counter
56
*)
57
node  Enabled_Counter_99_939(In1_1 : real;
58
	__time_step : real;
59
	__nb_step : int;)
60
returns(Out1_1 : real;
61
	Out2_1 : real;);
62
var Add_1 : real;
63
	UnitDelay_1 : real;
64
let
65
	Add_1 = 0.0 + In1_1 + UnitDelay_1;
66
	UnitDelay_1 = (0.0 -> (pre Add_1));
67
	Out1_1 = Add_1;
68
	Out2_1 = UnitDelay_1;
69
tel
70

    
71
node  case_held_held_held_116_903_triggeredSS(Cpre_compx_1 : real;
72
	Enable_1 : real;
73
	_isEnabled : bool;
74
	_isTriggered : bool;
75
	__time_step : real;
76
	__nb_step : int;)
77
returns(Ccor_x_1 : real;
78
	pre_x_1 : real;
79
	Out1_1 : real;);
80
var pre_Ccor_x_1 : real;
81
	pre_pre_x_1 : real;
82
	pre_Out1_1 : real;
83
	_isTriggered_clock : bool clock;
84
let
85
	pre_Ccor_x_1 = if (__nb_step > 0) then
86
		(pre Ccor_x_1)
87
	    else 0.0;
88
	pre_pre_x_1 = if (__nb_step > 0) then
89
		(pre pre_x_1)
90
	    else 0.0;
91
	pre_Out1_1 = if (__nb_step > 0) then
92
		(pre Out1_1)
93
	    else 0.0;
94
	_isTriggered_clock = _isTriggered;
95
	(Ccor_x_1, pre_x_1, Out1_1) = (merge _isTriggered_clock 
96
		(true -> case_held_held_held_116_903((Cpre_compx_1 when _isTriggered_clock), (Enable_1 when _isTriggered_clock), (__time_step when _isTriggered_clock), (__nb_step when _isTriggered_clock))) 
97
		(false -> (pre_Ccor_x_1, pre_pre_x_1, pre_Out1_1) when false(_isTriggered_clock)));
98
tel
99

    
100
(*
101
Original block name: TriggeredEnabled_Subsystem_PP/case_held_held_held
102
*)
103
node  case_held_held_held_116_903_condExecSS(Cpre_compx_1 : real;
104
	Enable_1 : real;
105
	_isEnabled : bool;
106
	_isTriggered : bool;
107
	__time_step : real;
108
	__nb_step : int;)
109
returns(Ccor_x_1 : real;
110
	pre_x_1 : real;
111
	Out1_1 : real;);
112
var pre_Ccor_x_1 : real;
113
	pre_pre_x_1 : real;
114
	pre_Out1_1 : real;
115
	_isEnabled_clock : bool clock;
116
let
117
	pre_Ccor_x_1 = if (__nb_step > 0) then
118
		(pre Ccor_x_1)
119
	    else 0.0;
120
	pre_pre_x_1 = if (__nb_step > 0) then
121
		(pre pre_x_1)
122
	    else 0.0;
123
	pre_Out1_1 = if (__nb_step > 0) then
124
		(pre Out1_1)
125
	    else 0.0;
126
	_isEnabled_clock = _isEnabled;
127
	(Ccor_x_1, pre_x_1, Out1_1) = (merge _isEnabled_clock 
128
		(true -> case_held_held_held_116_903_triggeredSS((Cpre_compx_1 when _isEnabled_clock), (Enable_1 when _isEnabled_clock), (_isEnabled when _isEnabled_clock), (_isTriggered when _isEnabled_clock), (__time_step when _isEnabled_clock), (__nb_step when _isEnabled_clock))) 
129
		(false -> (pre_Ccor_x_1, pre_pre_x_1, pre_Out1_1) when false(_isEnabled_clock)));
130
tel
131

    
132
(*
133
Original block name: TriggeredEnabled_Subsystem_PP/case_held_held_held
134
*)
135
node  case_held_held_held_116_903(Cpre_compx_1 : real;
136
	Enable_1 : real;
137
	__time_step : real;
138
	__nb_step : int;)
139
returns(Ccor_x_1 : real;
140
	pre_x_1 : real;
141
	Out1_1 : real;);
142
var Add_1 : real;
143
	UnitDelay_1 : real;
144
let
145
	Add_1 = 0.0 + Cpre_compx_1 + UnitDelay_1;
146
	UnitDelay_1 = (0.0 -> (pre Add_1));
147
	Ccor_x_1 = Add_1;
148
	pre_x_1 = UnitDelay_1;
149
	Out1_1 = Enable_1;
150
tel
151

    
152
(*
153
Original block name: TriggeredEnabled_Subsystem_PP
154
*)
155
node  TriggeredEnabled_Subsystem_PP(In1_1 : real;
156
	Enable_1 : real;
157
	Trigger_1 : real;)
158
returns(Out1_1 : real;
159
	Out2_1 : real;
160
	Out4_1 : real;
161
	pre_Out1_1 : real;
162
	Out8_1 : real;);
163
var ExecutionCond_of_Enabled_Counter_99_939 : bool;
164
	TriggerCond_of_Enabled_Counter_99_939 : bool;
165
	EnableCond_of_Enabled_Counter_99_939 : bool;
166
	Enabled_Counter_1 : real;
167
	Enabled_Counter_2 : real;
168
	ExecutionCond_of_case_held_held_held_116_903 : bool;
169
	TriggerCond_of_case_held_held_held_116_903 : bool;
170
	EnableCond_of_case_held_held_held_116_903 : bool;
171
	case_held_held_held_1 : real;
172
	case_held_held_held_2 : real;
173
	case_held_held_held_3 : real;
174
	__time_step : real;
175
	__nb_step : int;
176
let
177
	EnableCond_of_Enabled_Counter_99_939 = (Enable_1 > 0.0);
178
	TriggerCond_of_Enabled_Counter_99_939 = (false -> ((Trigger_1 > 0.0) and (not (pre (Trigger_1 > 0.0)))));
179
	ExecutionCond_of_Enabled_Counter_99_939 = (EnableCond_of_Enabled_Counter_99_939 and TriggerCond_of_Enabled_Counter_99_939);
180
	(Enabled_Counter_1, Enabled_Counter_2) = Enabled_Counter_99_939_condExecSS(In1_1, EnableCond_of_Enabled_Counter_99_939, TriggerCond_of_Enabled_Counter_99_939, __time_step, __nb_step);
181
	EnableCond_of_case_held_held_held_116_903 = (Enable_1 > 0.0);
182
	TriggerCond_of_case_held_held_held_116_903 = (false -> ((Trigger_1 > 0.0) and (not (pre (Trigger_1 > 0.0)))));
183
	ExecutionCond_of_case_held_held_held_116_903 = (EnableCond_of_case_held_held_held_116_903 and TriggerCond_of_case_held_held_held_116_903);
184
	(case_held_held_held_1, case_held_held_held_2, case_held_held_held_3) = case_held_held_held_116_903_condExecSS(In1_1, Enable_1, EnableCond_of_case_held_held_held_116_903, TriggerCond_of_case_held_held_held_116_903, __time_step, __nb_step);
185
	Out1_1 = Enabled_Counter_1;
186
	Out2_1 = Enabled_Counter_2;
187
	Out4_1 = case_held_held_held_1;
188
	pre_Out1_1 = case_held_held_held_2;
189
	Out8_1 = case_held_held_held_3;
190
	__time_step = (0.0 -> ((pre __time_step) + 0.20));
191
	__nb_step = (0 -> ((pre __nb_step) + 1));
192
tel
193